Multi-Deck Memory Bus Configuration for Die Size Reduction
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Solution Overview
Problem
Existing multi-deck non-volatile memory architectures face challenges in scaling down to smaller sizes and reducing energy consumption while maintaining effective hardware circuitry, leading to increased costs and complexity in memory device design.
Innovation Solution
The implementation of an improved wordline bus and bitline bus configuration, where these buses are positioned over the junctions between memory tiles and termination tiles, allowing for reduced hardware circuitry and simplified data shifting with limited data shifting directions, resulting in a more consistent timing and smaller die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory device scaling is continued, then memory density increases, but scaling limitations and manufacturing complexity increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory architecture to three-dimensional vertical stacking with multiple decks (e.g., four decks) positioned at different heights. Memory cells are arranged in vertical columns spanning multiple decks, enabling increased storage density without proportionally increasing manufacturing complexity by utilizing the vertical dimension for cell arrangement and wordline stacking.
2Quantity of substance
If multi-deck non-volatile memory architecture is implemented, then memory capacity increases, but hardware circuitry size increases
Solution Approach 1:
The patent implements shared wordline busses that serve multiple decks simultaneously. A single wordline bus can activate wordlines across different decks (e.g., Deck 0 through Deck 3) by applying voltage to vertically stacked wordlines. This multi-functional approach allows one bus structure to control memory cells in multiple decks, reducing the need for separate dedicated wordline busses for each deck and thereby reducing overall hardware circuitry size while maintaining high memory capacity.
3Adaptability or versatility
If more driver circuits are added to support multiple decks, then memory accessibility improves, but device size increases
Solution Approach 1:
The patent combines driver circuit functionality across multiple decks by implementing shared wordline busses and bitline busses that serve multiple decks. Instead of having separate driver circuits for each deck, the architecture merges control functions so that a single driver can control wordlines or bitlines across multiple decks through the shared bus structure, thereby maintaining full memory accessibility while reducing the total number of driver circuits and overall device size.
4Ease of manufacture
If hardware circuitry is reduced, then device cost decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the memory architecture into discrete decks (e.g., Deck 0, Deck 1, Deck 2, Deck 3) that can be manufactured and stacked independently. Each deck contains memory cells, wordlines, and bitlines that are self-contained units. This segmentation allows for standardized manufacturing processes for each deck layer, reducing the need for highly precise alignment across the entire multi-deck structure and thereby reducing device cost while maintaining manufacturability.
Data Source
AI summary
Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.