Memory Bus Divider Unit for Impedance Matching and Signal Isolation
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Solution Overview
Problem
Increasing system speeds in digital systems are hindered by bandwidth limitations in memory buses, which cannot be effectively addressed by simply increasing physical width or clock speed due to impedance differences and signal isolation issues.
Innovation Solution
The implementation of a divider unit configured to match impedance and provide signal isolation between memory units and the memory bus, using a combination of passive and active elements, such as transmission line transformers and resistances, to enhance bandwidth performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the physical width of the bus is increased to increase bandwidth, then the bandwidth is improved, but the layout space on the device is strictly limited due to decreasing physical dimensions
Solution Approach 1:
The bus interface is segmented into multiple independent channels, each operating at lower speed but collectively providing high bandwidth. This allows the system to achieve high productivity without requiring a single wide bus that would consume excessive layout space.
Solution Approach 2:
Instead of increasing bandwidth by widening the bus in one dimension, the patent uses multiple narrower channels operating in parallel across time and space dimensions, achieving the same bandwidth effect without the space penalty of a single wide bus.
2Productivity
If the clock speed of the bus is increased to increase bandwidth, then the bandwidth is improved, but impedance differences cause undesired signal reflections that adversely affect performance
Solution Approach 1:
The patent changes the operating parameters of each channel to lower clock speeds, which reduces signal reflections and improves reliability while maintaining high bandwidth through parallel channel operation. This parameter change resolves the contradiction between speed and signal integrity.
3Productivity
If the clock speed of the bus is increased to increase bandwidth, then the bandwidth is improved, but signal isolation problems arise as operational frequencies are further increased
Solution Approach 1:
By segmenting the bus into multiple independent channels, each channel operates at lower frequencies that avoid signal isolation problems while the collective bandwidth matches or exceeds that of a single high-speed channel.
Solution Approach 2:
The patent introduces intermediary components such as isolators and impedance matching networks between channels to prevent signal interference, allowing multiple channels to operate in close proximity without harmful interactions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly enhances memory system bandwidth by ensuring matched impedance and reducing signal attenuation, thereby improving overall system performance.
Implementation Method 1
a divider unit coupled to the bus and the memory units. The divider unit is operable to match an impedance of the memory units to an impedance of the bus
Implementation Method 2
The divider unit is operable to match an impedance of the memory units to an impedance of the bus, while providing for signal isolation between the memory units
Data Source
AI summary
Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.