Memory Bus Duty Cycle Calibration Using Delay-Tap Measurement
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Solution Overview
Problem
The challenge in data storage devices, such as SSDs, is the difficulty in dynamically calibrating the clock duty cycle due to environmental changes like temperature and supply voltage, which limits system performance and requires costly design margins and disruptive reconfiguration processes.
Innovation Solution
A measuring circuit comprising flip flop registers and delay taps is used to dynamically monitor and adjust the clock duty cycle in real-time, allowing for continuous operation without stopping the device, by inputting the clock signal directly and through delay taps to determine and calibrate the duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock duty cycle is calibrated at manufacturing, then device performance can be optimized, but larger design margins are required which increase costs and reduce device performance
Solution Approach 1:
The patent applies preliminary action by pre-configuring the measuring circuit with delay taps and flip-flop registers during manufacturing to enable future dynamic measurements. The circuit is prepared in advance with the necessary components (delay elements, flip-flops, and logic) so that when the device operates, the duty cycle can be measured immediately without requiring additional design margins or complex preliminary calibration procedures.
2Measurement precision
If the clock duty cycle is measured at manufacturing, then device configurations can be tuned, but potential changes to environmental conditions must be taken into account which reduces accuracy and requires additional margins
Solution Approach 1:
The patent applies dynamics by implementing a measuring circuit that continuously monitors the clock duty cycle during actual device operation rather than relying on static manufacturing measurements. The circuit dynamically adapts to changing environmental conditions (temperature, voltage) by real-time measurement using delay taps and flip-flop registers, allowing the system to adjust to environmental variations without requiring additional design margins.
3Reliability
If other clock duty cycle calibrations are performed, then the storage device can be reconfigured, but the device must stop operation which prohibits use until reconfiguration is complete
Solution Approach 1:
The patent applies continuity of useful action by enabling duty cycle measurement and calibration to occur during normal device operation. The measuring circuit is integrated into the operational path, allowing the device to continue processing data while the duty cycle is being monitored and adjusted. This eliminates downtime associated with traditional calibration methods that require stopping device operation.
4Productivity
If the clock frequency is increased to improve device performance, then system performance improves, but bus signal characteristics degrade which limits maximal clock frequency
Solution Approach 1:
The patent applies feedback by using the measuring circuit to continuously monitor bus signal characteristics (setup time, hold time) during high-frequency operation. The delay taps and flip-flop registers provide real-time feedback on whether the clock frequency is causing signal degradation, allowing the system to dynamically adjust the clock frequency to maintain optimal performance without exceeding reliability thresholds.
Data Source
AI summary
A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.