Memory Data Bus ECC for Noise-Resilient Flash Transmission

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Solution Overview

Problem

In electrically noisy environments, such as automobiles and aircraft, the integrity of data buses in flash memory systems is compromised due to noise interference, necessitating enhanced methods to ensure reliable data transmission.

Innovation Solution

Implementing an error detection and correction algorithm (EDAC) that generates error correction code (ECC) data, which is transmitted alongside the data and stored in the memory array, allowing the memory device to correct errors and improve data bus integrity, with an enable/disable flag controlling the correction process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error detection and correction algorithm (EDAC) is implemented to improve data bus integrity, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata bus integrityVSAvoidalgorithm complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary EDAC algorithm layer between the data bus and memory operations. This intermediary computes error correction codes (ECC) for outgoing data and verifies incoming data, acting as a mediator that protects against noise-induced errors without requiring fundamental changes to the data bus infrastructure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The EDAC algorithm performs preliminary error correction by computing ECC values before data transmission and preparing correction patterns in advance. During write operations, the algorithm pre-calculates ECC for the data to be stored, and during read operations, it pre-prepares correction logic, thereby resolving errors before they affect data integrity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If EDAC algorithm is used to correct errors in noisy environments, then reliability is improved, but loss of time increases due to additional processing

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoiderror correction processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs error correction computations in advance during write operations, calculating ECC values before data is stored in memory. This preliminary computation allows read operations to simply verify and correct errors without extensive processing delays, as the correction patterns are already prepared.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The EDAC algorithm implements self-service error correction by automatically detecting, correcting, and handling errors without external intervention. The system autonomously manages the entire error correction process, including computing ECC, detecting errors during transmission, and applying corrections, thereby minimizing the perceived processing time for higher-level operations.

Inventive Principle:
Principle #25Self-service

3Reliability

If ECC data is appended to data packets for error correction, then data bus integrity is improved, but quantity of substance increases due to additional data bits

Engineering Contradiction:
Improvedata bus integrityVSAvoiddata packet size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent dynamically adjusts the amount of ECC data appended to data packets based on the noise level and reliability requirements of the communication channel. In noisy environments, more ECC bits are added for robust error correction, while in cleaner environments, fewer ECC bits are used, thereby optimizing the balance between reliability and data packet size.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system applies partial error correction by adding only the minimum necessary ECC data to protect against the expected noise level. Rather than using full-strength error correction for all transmissions, the algorithm calculates the appropriate level of protection needed, adding just enough ECC bits to achieve the desired reliability without excessive overhead.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9323608B2Integrity of a data bus
Publication Date: 2016.04.26 MICRON TECHNOLOGY INC
  • US9323608B2 patent drawing
  • US9323608B2 patent drawing
  • US9323608B2 patent drawing

AI summary

A method for improving data bus integrity includes a selectable data bus integrity feature that can improve the integrity of a data bus in a memory system. An external controller generates error correction data in response to associated data to be transmitted. The error correction data is divided into multiple data packets and appended to the corresponding data for transmission over the data bus. The memory device can use the ECC data, if the feature is enabled, to attempt to correct the corresponding data and store both the corrected data and the ECC data.