Multi-Chip Memory Data Bus Transfer With ECC Pre-Correction
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Solution Overview
Problem
Multi-chip memory systems face inefficiencies in data transfer between memory devices, particularly due to the need for data to pass through a memory controller, which can slow down operations and introduce errors.
Innovation Solution
A multi-chip memory system design that enables direct data transfer between nonvolatile memory devices using a memory controller to manage enable signals, control signals, and error correction, allowing data to be shared directly on a data bus without passing through the controller, and includes error detection and correction mechanisms to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred through the memory controller between memory devices, then the memory controller can manage and control the data transfer process, but the data transfer rate is reduced and transfer time is increased
Solution Approach 1:
The patent extracts the data transfer path from the memory controller by enabling direct data bus connection between memory devices. The memory controller is excluded from the direct data transfer path, allowing data to move directly between memory devices without passing through the controller, thus resolving the contradiction between controller management and transfer speed.
Solution Approach 2:
The patent introduces a data bus as an intermediary component that enables direct communication between memory devices. This intermediary allows data to be transferred directly between memory devices while the memory controller maintains overall system control through separate control signals, resolving the contradiction between centralized control and direct data transfer.
2Reliability
If data is transferred through the memory controller, then error detection and correction can be performed, but the transfer process becomes more complex and time-consuming
Solution Approach 1:
The patent implements preliminary error correction by having the source memory device perform error correction on data before transferring it to the destination memory device. The error correcting code (ECC) circuit in the source device corrects errors in advance, eliminating the need for time-consuming error checking and correction during the transfer process through the memory controller.
3Productivity
If memory devices are enabled simultaneously for direct data transfer, then data transfer rate is improved, but the complexity of managing enable signals and control increases
Solution Approach 1:
The patent merges the control of multiple memory devices by using a unified enable signal mechanism. The memory controller generates enable signals that are simultaneously applied to both source and destination memory devices, coordinating their operation for direct data transfer. This merging of control mechanisms simplifies the management of simultaneous device enabling while maintaining high transfer rates.
Data Source
AI summary
A multi-chip memory system comprises source and target memory devices, a memory controller configured to control operations of the source and target memory devices, and a data bus configured for data transfer of the memory controller and the source and target memory devices. The memory controller controls the source memory device to perform a read operation to output data to the data bus. Concurrently, the memory controller controls the target memory device to store the data from the data bus.