Interface Apparatus for Memory Bus Header Ordering
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Solution Overview
Problem
Conventional Network-on-Chip (NoC) configurations face challenges in maintaining proper correspondence between response headers and response data when the order of requests is changed, leading to potential system failures and performance declines.
Innovation Solution
An interface apparatus that includes a de-packetizing processor, a header generator, a packetizing processor, and a header order controller, which manages response headers to ensure proper ordering and transmission, even when the order of requests is altered, allowing for increased memory access efficiency without increasing operating frequency or bus width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the order of requests is changed to increase memory access efficiency, then memory access efficiency is improved, but the correspondence between response headers and response data may be lost
Solution Approach 1:
The header generator creates and stores response headers in advance based on the original request order, before the memory access completes. This preliminary generation of headers with their original ordering information allows the system to later match them with responses in the correct sequence, even when memory access order changes
Solution Approach 2:
The interface apparatus acts as an intermediary between the memory controller and the bus network. It receives responses from the memory controller, matches them with the pre-generated headers using the header generator and header order controller, and transmits them in the correct order. This intermediary function preserves the correspondence between headers and data despite order changes in memory access
2Power
If the operating frequency and bus width are increased to improve bandwidth, then bandwidth is improved, but device complexity and power consumption increase
Solution Approach 1:
The system dynamically changes the order of memory accesses based on arbitration results without requiring increases in operating frequency or bus width. The header order controller dynamically adjusts the transmission order of responses to match the dynamic access patterns, achieving efficient bandwidth utilization through flexible ordering rather than brute-force increases in speed or width
Solution Approach 2:
The invention changes the parameter of request/response ordering without changing fundamental hardware parameters like frequency or bus width. By modifying the sequence parameter and using intelligent header management, the system achieves improved bandwidth efficiency through software/firmware control rather than hardware scaling
Data Source
AI summary
An exemplary interface apparatus includes: a header generator which receives, in a first order, a plurality of request headers extracted from a plurality of request packets, generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order; and a header order controller which controls the header generator so that if the plurality of request data have been transmitted to the memory in a second order, the respective response headers are read in the second order.