Dynamic Memory Bus Line Allocation for Data and Control Traffic

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Solution Overview

Problem

Data buses in memory systems often experience underutilization and inefficiency due to fixed configurations, leading to increased latency and system performance issues, particularly when the ratio of control bits to data bits changes, resulting in unnecessary footprint expansion and reduced complexity.

Innovation Solution

A memory controller dynamically configures transmission lines of a data bus to allocate resources based on the quantity of control and data bits, allowing some lines to carry control traffic and others to carry data traffic, with error protection mechanisms like parity or CRC to ensure reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If transmission lines are allocated for control traffic, then control communication reliability is ensured, but data bus utilization decreases

Engineering Contradiction:
Improvecontrol communication reliabilityVSAvoiddata bus utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic configuration of transmission lines where the memory controller can switch between dedicated control bus mode and shared data/control bus mode based on operational needs. This allows the system to adapt the bus configuration dynamically, using dedicated control lines when reliability is critical and sharing lines with data traffic when bus utilization should be maximized, thereby resolving the contradiction between reliability and productivity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent enables transmission lines to serve multiple functions by allowing them to be configured as either control-only lines or shared data/control lines. The same physical infrastructure can universally handle both control traffic and data traffic depending on the configuration, eliminating the need for permanently dedicated control lines and improving overall bus utilization while maintaining reliability when needed

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If more transmission lines are allocated for control traffic, then control traffic capacity increases, but system footprint increases

Engineering Contradiction:
Improvecontrol traffic capacityVSAvoidsystem footprint
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The system dynamically adjusts the number of control transmission lines based on actual control traffic requirements. During operations requiring high control traffic capacity, more lines are allocated; during data-intensive operations, fewer lines are used for control. This dynamic allocation allows the system to maintain adequate control capacity when needed while minimizing the footprint during data transfer operations

Inventive Principle:
Principle #15Dynamics

3Device complexity

If fixed bus configuration is used, then system complexity is reduced, but latency increases

Engineering Contradiction:
Improvesystem complexityVSAvoidlatency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent implements a dynamically reconfigurable bus system where the memory controller can switch between different bus configurations (dedicated control, shared data/control, data-only modes) based on operational requirements. This dynamic capability reduces latency by optimizing the bus configuration for current traffic patterns without significantly increasing system complexity, as the reconfiguration is managed through control logic that adapts to varying workload demands

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11086803B2Dynamically configuring transmission lines of a bus
Publication Date: 2021.08.10 MICRON TECHNOLOGY INC
  • US11086803B2 patent drawing
  • US11086803B2 patent drawing
  • US11086803B2 patent drawing

AI summary

Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, control bits) to be communicated with a second device over a data bus. The first device may partition the data bus into a first set of transmission lines (e.g., based on the quantity of data bits) and a second set of transmission lines (e.g., based on the quantity of control bits). The first device may communicate the quantity of data bits over the first set of transmission lines and communicate the quantity of control bits over the second set of transmission lines. In some cases, the first device may repartition the data bus based on different quantities of data bits and control bits to be communicated with the second device at a different time.