Runtime Memory Bus Line Reassignment for Warm Reset Security
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Solution Overview
Problem
Warm reboots in computing devices pose security risks due to retained memory states, allowing cyber threats to exploit vulnerabilities and persist on the system.
Innovation Solution
A runtime memory system that utilizes unpredictable multiplexing of memory bus lines, dynamically reassigning data and/or address bus connections between a processor and its runtime memory during warm reset operations, effectively changing the physical memory topology and neutralizing memory-resident malicious software.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If warm reboot is used to restart the system, then system downtime is reduced and operations continue, but memory states are retained allowing security vulnerabilities to persist
Solution Approach 1:
The patent applies dynamics by making the memory bus line assignments changeable and unpredictable during warm reboot. Instead of retaining static memory mappings, the system dynamically reassigns bus lines (e.g., data bus line 01 reassigned to link with bus line 23) so that memory locations change physically, neutralizing persistent malicious software while maintaining operational continuity
Solution Approach 2:
The patent changes the parameter of memory bus line assignments from fixed to variable. By implementing unpredictable multiplexing that randomly remaps bus lines during warm reboot, the system alters the physical memory topology parameter, ensuring that exploit code cannot persist across the reboot while maintaining standard memory operations
2Object-affected harmful factors
If cold reboot is used to clear memory and reset hardware, then security risks are reduced by clearing exploits, but system downtime increases and all hardware states are reset
Solution Approach 1:
The patent makes the memory mapping dynamic and unpredictable during warm reboot, achieving security clearance without full cold reboot. By randomly remapping bus lines (e.g., reassigning data bus line 01 to bus line 23), the system dynamically changes physical memory topology to neutralize exploits while avoiding complete hardware reset and extended downtime
3Reliability
If memory bus line assignments are made fixed and predictable, then memory operations are simple and reliable, but malicious software can reliably target specific memory locations
Solution Approach 1:
The patent implements feedback by having the memory system automatically detect warm reboot conditions and respond by randomly remapping bus lines. This feedback mechanism ensures that any attempt by malicious software to persist in memory is countered by the system's automatic topology change, maintaining security without affecting normal memory operation reliability
Data Source
AI summary
This document describes technology for a runtime memory system that utilizes unpredictable multiplexing of memory bus lines. The technology dynamically reassigns data and/or address bus connections between a processor and its runtime memory during warm reset operations. The bus line assignments are made through a multiplexing mechanism—for example, data bus line 01 from the processor may be reassigned to link with bus line 23 at the runtime memory system interface. When a warm reset occurs, the physical mapping of memory locations changes due to this bus line reassignment. The system maintains standard memory operations while implementing this dynamic bus line configuration. Malicious software relying upon memory-resident exploit becomes inoperable after warm reset due to the changed physical memory topology created by the bus line reassignment process.