Semiconductor Memory Bus Node Discharge for Peak Current Reduction
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing peak current consumption during data transmission between page buffers and cache latches, which affects efficiency and performance.
Innovation Solution
Incorporating a bus node setting component that discharges the bus node before data transmission between page buffers and cache latches, allowing the bus node voltage to swing between a power voltage and 0V, thereby reducing peak current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bus node voltage swings between power voltage and 0V during data transmission, then data transmission between page buffer and cache latch can be performed, but peak current consumption increases
Solution Approach 1:
The bus node is pre-charged to a voltage between 0V and power voltage before data transmission begins. This preliminary action reduces the voltage swing幅度 during actual data transmission, thereby reducing peak current consumption while maintaining reliable data transmission between the page buffer and cache latch
2Use of energy by moving object
If the bus node is discharged before data transmission, then peak current consumption is reduced, but additional control circuitry is required
Solution Approach 1:
The bus node setting component is designed to perform multiple functions: it charges the bus node to an intermediate voltage level, controls the discharge timing, and coordinates with the data transmission process. This multi-functional design reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while achieving peak current reduction
3Use of energy by moving object
If voltage swing width is minimized, then peak current consumption decreases, but data transmission speed may be affected
Solution Approach 1:
The bus node charging and discharging operations are performed in periodic cycles synchronized with data transmission requirements. The bus node is charged to the intermediate voltage level before transmission, maintains this level during transmission to reduce peak current, and is reset in preparation for the next transmission cycle. This periodic operation maintains data transmission speed while reducing peak current consumption
Data Source
AI summary
A semiconductor memory device includes: a memory cell for storing data; a page buffer connected to the memory cell through a bit line, to store data in the memory cell or read data from the memory cell; and a cache latch connected to the page buffer through a bus node. When bit data transmission operation between the page buffer and the cache latch is performed, the bus node is discharged before starting the bit data transmission operation.