Nonvolatile Memory Bus Precharge Segmentation
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Solution Overview
Problem
The bus precharge method in nonvolatile semiconductor memory is inefficient in reducing power consumption due to repeated charging and discharging of the data bus, especially in multi-valued memory systems where increased parasitic capacitance occurs, requiring all data bus capacitance to be charged regardless of data transfer direction.
Innovation Solution
The method involves dividing the data bus into two buses and using a clamp transistor between them, with the output side bus precharged to a potential lower than the input side bus, reducing the amount of charge needed and optimizing charging based on data transfer directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the bus precharge method is used for data transfer, then the circuit area is reduced, but power consumption increases due to repeated charging and discharging of the data bus
Solution Approach 1:
The data bus is divided into two separate buses: a first data bus connecting the sense amplifier to the data latch, and a second data bus connecting the data latch to the cache memory. This segmentation allows independent precharging of each bus segment, reducing the total capacitance that must be charged during data transfer operations.
Solution Approach 2:
The first data bus is precharged to a first potential and the second data bus is precharged to a second potential before data transfer operations. This preliminary precharging action ensures that the buses are ready for data transfer without requiring repeated charging and discharging, thereby reducing power consumption.
2Adaptability or versatility
If data latches are commonly connected to the data bus in multi-valued memory, then data transfer is enabled, but the data bus becomes longer and parasitic capacitance increases
Solution Approach 1:
The data bus is segmented into two separate buses with different precharge potentials. The first data bus connects the sense amplifier to the data latch, while the second data bus connects the data latch to the cache memory. This segmentation reduces the effective length and parasitic capacitance of each individual bus segment.
Solution Approach 2:
Different precharge potentials are applied to different segments of the data path. The first data bus is precharged to a first potential optimized for sense amplifier to data latch transfer, while the second data bus is precharged to a second potential optimized for data latch to cache memory transfer. This local optimization reduces overall parasitic capacitance effects.
3Reliability
If all parasitic capacitance of the data bus is charged, then complete data transfer is ensured, but power consumption increases regardless of data transfer direction
Solution Approach 1:
The data path is divided into two segmented buses with different precharge potentials. Only the necessary bus segments are fully charged based on the data transfer direction, while the other segment maintains a lower precharge potential, reducing overall power consumption while ensuring reliable data transfer.
Solution Approach 2:
Different precharge potentials (first potential and second potential) are applied to different bus segments based on the data transfer direction. This parameter change allows the system to optimize power consumption by charging only the necessary capacitance while maintaining data transfer reliability.
Data Source
AI summary
According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area.