Memory Data Bus Pulse Width Control Across Frequency Changes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory device circuits fail to automatically adjust the pulse width of the read/write strobe pulse signal in response to variations in operating frequency and voltage, requiring costly and time-consuming modifications during the FIB process.
Innovation Solution
A circuit with a pulse width adjusting mechanism that uses a first delay circuit and a NAND gate to adjust the pulse width based on the frequency of the clock signal, and further adjusts the delay time using external address signals, ensuring the pulse width remains optimal across varying frequencies and voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the pulse width of the read/write strobe pulse signal is fixed, then the circuit operation is simple, but the circuit cannot adapt to variations in operating frequency and voltage
Solution Approach 1:
The patent implements dynamic pulse width adjustment by introducing a delay circuit whose delay time is controlled by a control signal. This control signal is generated based on the operating frequency and voltage conditions, allowing the pulse width to dynamically adapt to different operating conditions rather than being fixed. The delay circuit modifies the pulse width of the read/write strobe signal in real-time according to the detected operating parameters.
Solution Approach 2:
The patent changes the pulse width parameter of the read/write strobe signal based on operating frequency and voltage conditions. By detecting these operating parameters and adjusting the delay time accordingly, the system optimizes the pulse width to maintain reliable operation across different frequency and voltage ranges without requiring complete circuit redesign.
2Reliability
If the pulse width is adjusted manually through FIB process, then the operation can be optimized for specific frequencies, but the process is costly and time-consuming
Solution Approach 1:
The patent implements self-adjustment by incorporating frequency and voltage detection circuits that automatically generate control signals for the delay circuit. The system detects its own operating conditions and autonomously adjusts the pulse width without requiring external manual intervention or FIB process tuning, thereby eliminating the time-consuming and costly manual optimization process.
Solution Approach 2:
The patent establishes a feedback mechanism where the operating frequency and voltage are detected, and this information is fed back to control the delay time of the pulse width adjustment circuit. This closed-loop feedback system ensures that the pulse width is continuously optimized based on actual operating conditions, maintaining reliability without manual intervention.
3Productivity
If the pulse width is made wider to improve data transfer, then the data transfer performance is improved, but the permissible range becomes narrower as operating frequency increases
Solution Approach 1:
The patent makes the pulse width dynamic rather than static by introducing a controllable delay circuit. The delay time is adjusted based on the operating frequency, allowing the pulse width to be wider at lower frequencies (improving data transfer) and appropriately narrowed at higher frequencies (maintaining operational flexibility). This dynamic adjustment resolves the contradiction between maximizing data transfer and maintaining adaptability across frequency ranges.
Data Source
AI summary
Provided is a circuit for controlling a data bus connecting a bitline sense amplifier to a data sense amplifier in accordance with a variation of an operating frequency of a memory device, being comprised of a pulse width adjusting circuit for varying a pulse width of an input signal in accordance with the operating frequency of the memory device after receiving the input signal, a signal transmission circuit for buffing a signal outputted from the pulse width adjusting circuit, and an output circuit for outputting a first signal to control the data bus in response to a signal outputted from the signal transmission circuit.