Memory Command Address Bus Utilization Refresh Embedding
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Solution Overview
Problem
Memory devices face inefficiencies in command/address bus utilization due to the need for multiple refresh single bank commands to refresh all memory banks, which consumes more bandwidth compared to a single refresh all banks command, reducing the available time for reading and writing data.
Innovation Solution
Embedding refresh single bank commands into other commands like read or write commands, allowing for reduced command/address bus bandwidth consumption by performing refresh operations concurrently with data operations, thereby keeping other memory banks available for access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple refresh single bank commands are used to refresh all memory banks, then data integrity is maintained, but command/address bus bandwidth consumption increases
Solution Approach 1:
The patent combines refresh operations with data access operations by embedding refresh single bank commands within read or write command sequences. This merging allows the memory device to perform refresh operations concurrently with data operations, maintaining data integrity while reducing the total bandwidth consumption of the command/address bus.
Solution Approach 2:
The patent enables continuous useful action by embedding refresh commands within existing data access cycles. Instead of separating refresh operations from data operations, the system maintains continuous productivity by performing refresh actions during otherwise idle or overlapping time periods within the data access timeline, ensuring no loss of data integrity while maximizing bus utilization efficiency.
2Reliability
If multiple refresh single bank commands are issued, then all memory banks are refreshed, but the time available for reading and writing data is reduced
Solution Approach 1:
The patent applies preliminary action by embedding refresh commands within the data access command sequence in advance. Refresh operations are performed proactively during the data access timeline rather than as separate subsequent operations, ensuring all memory banks are refreshed before data access needs arise, thus maintaining reliability without extending the data access time.
Solution Approach 2:
The patent merges refresh operations with data access operations by embedding refresh single bank commands within read or write command sequences. This combination allows the memory device to perform refresh operations concurrently with data operations, maintaining complete memory bank refresh while maximizing the time available for reading and writing data.
3Reliability
If refresh operations are performed separately from data operations, then memory banks are refreshed reliably, but command/address bus utilization efficiency decreases
Solution Approach 1:
The patent merges refresh operations with data access operations by embedding refresh single bank commands within read or write command sequences. This integration ensures reliable refresh operation completion while dramatically improving command/address bus utilization efficiency, as the same bus resources are used for both refresh and data operations simultaneously rather than sequentially.
Solution Approach 2:
The patent maintains continuous useful action on the command/address bus by embedding refresh commands within existing data access cycles. This approach ensures reliable refresh completion while maximizing bus utilization efficiency, as the bus remains continuously productive with no idle time dedicated solely to refresh operations.
Data Source
AI summary
Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.