Multi-Layer Memory Bus Segmentation for FIB Attack Resistance
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Solution Overview
Problem
Existing semiconductor devices lack effective protection against invasive attacks on the memory bus, allowing unauthorized entities to compromise and access secret data stored in memory, such as cryptographic keys, by using focused ion beam techniques to modify the memory bus signals.
Innovation Solution
Implementing a memory bus protection scheme where signals are distributed across multiple layers of the integrated circuit, with an intermediate group of signals vertically positioned between the initial and final groups, requiring multiple openings and probes to be created by an attacker, thereby exceeding the capacity of FIB techniques, and optionally encoding data with random values for additional security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory bus signals are transmitted using conventional single-layer routing, then the device structure remains simple and manufacturing is easier, but the memory bus becomes vulnerable to invasive attacks such as FIB techniques
Solution Approach 1:
The memory bus signals are segmented into multiple groups and routed through different metal layers. Specifically, first groups of signals are routed through a first metal layer, second groups of signals are routed through a second metal layer, and third groups of signals are routed through a third metal layer. This segmentation prevents attackers from compromising all signals through a single FIB attack on one layer.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar routing to three-dimensional multi-layer routing. By distributing signals across multiple vertical layers (first, second, and third metal layers), the routing structure adds a vertical dimension that increases the complexity and cost of invasive attacks, as attackers would need to create multiple openings through different layers.
2Object-affected harmful factors
If FIB techniques are used to compromise the memory bus, then attackers can retrieve secret data such as cryptographic keys, but the attack requires significant time and resources when multi-layer protection is implemented
Solution Approach 1:
By segmenting the memory bus signals across multiple metal layers, the patent forces attackers to perform multiple separate FIB operations to compromise all signal groups. Each layer requires a separate opening and probing operation, significantly increasing the time and resources required for a successful attack compared to single-layer routing.
Solution Approach 2:
The patent implements preliminary protective measures by pre-distributing signals across multiple layers before any attack occurs. This proactive segmentation creates inherent resistance to FIB attacks, making the attack process more complex and time-consuming before the attacker even begins their operation.
Data Source
AI summary
A first address bus may be located in an upper layer of an integrated circuit that is associated with a memory and a memory controller. The first address bus may receive a first portion of a memory address. A second address bus may be located in a lower layer of the integrated circuit where the second address bus is to receive a second portion of the memory address. Furthermore, a data bus may be located in an intermediate layer where the data bus is to receive data corresponding to the memory address from the memory and may transmit the data to the memory controller. The intermediate layer may be between the upper layer and the lower layer. A layout of the signals of the data bus may vertically overlap with a layout of signals of the first address bus and a layout of signals of the second address bus.