Intra-Package Memory Bus Structure for High-Speed Stacked Dies
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Solution Overview
Problem
Maintaining high throughput and maximizing interface speeds in stacked memory devices is challenging due to internal connection delays, CMOS process skew, and load capacitance effects that interfere with signal transmission, leading to timing failures and reduced throughput.
Innovation Solution
Implementing an intra-package bus that couples a primary die to multiple secondary dies within the memory package using an intra-package communication protocol that enables high concurrency with reduced capacitive loading, and utilizing a chip ID-based command packet structure to improve manufacturing efficiency and flexibility, allowing each die to independently process commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory dies are stacked to increase density, then memory capacity increases, but internal connection delays and capacitive loading increase causing timing failures
Solution Approach 1:
The patent segments the memory system into multiple independent dies (first die, second die, third die) that can be stacked vertically. Each die is a separate functional unit with its own memory cells and control logic, allowing the system to achieve high capacity through stacking while managing signal delays through segmented architecture and selective activation.
Solution Approach 2:
The patent implements preliminary action by pre-configuring multiple dies in a stacked arrangement with all necessary interconnections established before operation. The system prepares multiple memory banks across different dies in advance, enabling rapid data retrieval by selecting from pre-positioned storage locations without real-time configuration delays.
2Quantity of substance
If multiple memory dies are stacked to increase density, then memory capacity increases, but interface speed decreases due to capacitive loading
Solution Approach 1:
The patent segments the memory interface into multiple independent channels, each connecting to specific dies. This segmentation allows parallel data transmission across different dies simultaneously, maintaining high interface speed while accessing large capacity. The segmented architecture prevents capacitive loading from bottlenecking the entire interface.
Solution Approach 2:
The patent transitions from a two-dimensional planar memory layout to a three-dimensional stacked architecture. By stacking dies vertically in the Z-dimension, the system achieves higher capacity without proportionally increasing the capacitive load on the primary interface, as multiple dies can be accessed through parallel pathways and selective activation.
3Quantity of substance
If multiple memory dies are stacked to increase density, then memory capacity increases, but timing precision deteriorates due to CMOS process skew
Solution Approach 1:
The patent segments the timing control into die-specific control logic, with each die having its own timing management unit. This segmentation allows independent timing calibration for each die, compensating for CMOS process skew variations. Each die can be timed and synchronized independently, maintaining overall system timing precision despite manufacturing variations.
Solution Approach 2:
The patent applies local quality by implementing die-specific timing parameters and control characteristics. Each die in the stack can have customized timing settings optimized for its specific manufacturing variations and position in the stack. This localized timing control ensures that CMOS process skew does not propagate across the entire system, maintaining precision in each local region.
Data Source
AI summary
A packaged memory device can include a primary memory die coupled to a shared intra-package communication bus and coupled to an external host device using a host interface bus, and the host interface bus can include a host clock channel. The memory device can include multiple secondary dies coupled to the intra-package communication bus, and each of the secondary dies can be configured to receive the same messages from the primary memory die using the intra-package communication bus. The primary memory die can send a first message to, or receive a first message from, a particular one of the secondary dies using the intra-package communication bus, and the first message can include a first chip identification field that exclusively indicates the particular one of the secondary dies.