Memory Bus Management via Sub-Operation Lists

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Solution Overview

Problem

In nonvolatile memory systems, shared memory buses can become bottlenecks due to inefficient management, particularly when polling for available memory dies, leading to delays and suboptimal use of resources.

Innovation Solution

Implementing a memory bus management scheme that maintains two lists of sub-operations, where one list contains unreleased operations and the other contains released operations, allowing for continuous execution without polling until the released list is empty, and then polling to identify available dies to move operations from the unreleased list to the released list, optimizing bus usage and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If polling is used to identify available memory dies, then the memory bus can detect ready dies, but the memory bus becomes unavailable for other purposes during polling

Engineering Contradiction:
Improvedetection of ready diesVSAvoidmemory bus utilization
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The system performs preliminary actions by maintaining a list of sub-operations that are ready to be executed (released sub-operations) before polling is needed. When the memory bus becomes available, it checks this pre-prepared list and executes operations without needing to poll for availability, thus eliminating the conflict between detection and utilization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The polling function is extracted and separated from the main execution flow. Polling is performed only when the list of released sub-operations is empty, rather than continuously during execution. This separation allows the memory bus to focus on execution when possible and only engage in polling when necessary.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If sub-operations are executed continuously without polling, then memory bus utilization improves, but the system may miss opportunities to execute operations on available dies

Engineering Contradiction:
Improvememory bus utilizationVSAvoidexecution opportunity detection
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system implements feedback by continuously monitoring the list of released sub-operations. When this list becomes empty, the system triggers a polling action to check for new available dies, which may generate new released sub-operations to add to the list. This feedback loop ensures the system never misses execution opportunities while maintaining continuous operation when possible.

Inventive Principle:
Principle #23Feedback

3Reliability

If polling occurs frequently to ensure no execution opportunities are missed, then execution reliability improves, but polling delays increase and reduce overall system performance

Engineering Contradiction:
Improveexecution opportunity detectionVSAvoidpolling delays
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Instead of continuous or frequent polling, the system uses periodic polling that is triggered only when the list of released sub-operations is empty. This periodic action occurs at the necessary moments rather than continuously, eliminating unnecessary polling delays while still ensuring execution opportunities are not missed.

Inventive Principle:
Principle #19Periodic action

4Stability of the object's composition

If the memory bus waits for die availability before executing operations, then proper timing is ensured, but the memory bus remains idle during waiting periods

Engineering Contradiction:
Improvetiming synchronizationVSAvoidmemory bus utilization
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The system performs preliminary actions by identifying and releasing sub-operations in advance when dies become available, rather than waiting until execution time. This allows the memory bus to have operations ready to execute immediately when it becomes available, eliminating idle waiting periods while maintaining proper timing synchronization.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9734098B2Memory bus management
Publication Date: 2017.08.15 SANDISK TECHNOLOGIES LLC
  • US9734098B2 patent drawing
  • US9734098B2 patent drawing
  • US9734098B2 patent drawing

AI summary

A method of managing a memory bus includes identifying sub-operations required for execution of commands, maintaining a list of released sub-operations containing only released unexecuted sub-operations directed to individual dies that are identified as available, accessing the dies until the list is empty, subsequently, polling to identify dies that are available, and subsequently resuming accessing the dies by executing only sub-operations from the list until the list is empty.