Configurable Memory Bus Switch for Blade Server CPU Adaptation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computer systems with limited board space and thermal capabilities, such as blade servers, the available memory capacity is restricted when using a single CPU, and existing solutions are inflexible and costly, requiring additional hardware or dual CPU designs.
Innovation Solution
A memory switching data processing system with a flexibly configurable memory bus switch that adapts to either a single CPU or dual CPU configuration, allowing memory banks to be shared or isolated based on CPU presence, using switch segments and transistors to manage memory bus connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single CPU is installed in the system, then the system is limited to one-half of the memory capacity it could use, but the available board space and thermal capabilities are constrained
Solution Approach 1:
The patent implements a dynamic memory switch that can change its configuration based on the number of CPUs installed. The switch has multiple states: when one CPU is installed, the switch connects that CPU to both memory banks, enabling access to full memory capacity. When two CPUs are installed, the switch reconfigures to connect each CPU to its own dedicated memory bank. This dynamic reconfiguration resolves the contradiction by adapting the memory allocation to the actual hardware configuration.
Solution Approach 2:
The memory switch serves multiple functions depending on the system configuration. It can operate in a shared mode where one CPU accesses both memory banks, or in a dedicated mode where two CPUs each access their own memory bank. This multi-functionality allows the same hardware design to support different CPU configurations without requiring additional memory modules, thereby increasing adaptability while maintaining memory capacity.
2Quantity of substance
If another blade server is designed for single CPU applications, then single CPU memory capacity is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent creates a universal blade server design that works for both single-CPU and dual-CPU configurations. The memory switch is designed to automatically detect the number of CPUs installed and reconfigure accordingly. This eliminates the need for separate single-CPU and dual-CPU blade server designs, reducing device complexity and manufacturing costs while maintaining full memory capacity for single-CPU applications.
Solution Approach 2:
The dynamic reconfiguration capability of the memory switch allows the same hardware platform to adapt to different CPU configurations. The switch can be programmed or automatically configured to provide optimal memory access patterns whether one or two CPUs are installed, eliminating the need for multiple specialized hardware designs and reducing overall system complexity.
3Adaptability or versatility
If a two-piece blade with single and dual CPU versions is designed, then adaptability is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent implements a universal memory switch design that provides adaptability to both single-CPU and dual-CPU configurations within a single blade server platform. The switch can be configured through software or firmware to operate in different modes, eliminating the need to manufacture separate single-CPU and dual-CPU blade versions. This single-platform approach significantly reduces manufacturing costs while maintaining full adaptability.
Solution Approach 2:
The memory switch's dynamic reconfiguration capability allows the same physical hardware to serve multiple CPU configurations. Rather than manufacturing different hardware versions, the system uses a single design with programmable memory allocation that adapts at runtime based on the detected CPU configuration, reducing manufacturing complexity and cost.
Data Source
AI summary
A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.