Memory Module Bus Switching for Higher Bandwidth Capacity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the capacity of memory apparatuses and/or memory packages increases, data load increases, operation speed is limited, and operation timing varies, leading to a decrease in effective bandwidth between the host apparatus and the memory module.
Innovation Solution
A memory module configuration with a module substrate, memory packages, and a module controller circuit, where memory chips are accessed via chip selection signals and data pads are coupled in common to signal transmission lines, with the module controller connecting the data bus to specific signal transmission lines based on these signals, reducing load and improving data signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacity of memory apparatuses and/or memory packages is increased, then data capacity is improved, but data load increases and operation speed is limited
Solution Approach 1:
The memory module is divided into multiple independent memory packages (first and second memory packages), each with its own data transmission lines. This segmentation allows parallel data access across multiple packages, increasing overall data capacity while maintaining operation speed by avoiding centralized bottlenecks.
Solution Approach 2:
A module controller circuit is introduced as an intermediary between the host apparatus and multiple memory packages. The controller manages data routing and timing for each package independently, coordinating access to prevent timing conflicts and maintain operation speed while handling increased data capacity from multiple packages.
2Quantity of substance
If the number of stacked dies is increased, then data capacity is improved, but operation timing varies and effective bandwidth decreases
Solution Approach 1:
Instead of stacking multiple dies vertically in a single package, the invention segments memory capacity across multiple separate packages mounted on the module substrate. Each package can be accessed independently with consistent timing, avoiding the timing variations that occur in stacked die configurations where signal paths have different lengths.
Solution Approach 2:
The invention transitions from vertical stacking (z-dimension) to horizontal arrangement (x-y plane) of memory packages on the module substrate. This dimensional change allows all packages to be accessed simultaneously with uniform timing characteristics, maintaining effective bandwidth while increasing total data capacity through parallel access to multiple packages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration efficiently reduces loading, mitigates speed reduction, and enhances data signal integrity by electrically connecting memory chips using bonding wires, thereby improving the operation speed and bandwidth between the host apparatus and the memory module.
Implementation Method 1
electrically connecting memory chips using bonding wires
Data Source
AI summary
A memory module may include a module substrate, a first memory package, a second memory package, and a module controller circuit. The module substrate may include first signal transmission lines and second signal transmission lines. Memory chips of the first memory package may be coupled in common to the first signal transmission lines. Memory chips of the second memory package may be coupled in common to the second signal transmission lines. The module controller circuit may connect a data bus to one of the first signal transmission lines and the second signal transmission lines based on a chip selection signal.