Memory Bus Tristate Circuit for Power-Up Signal Integrity
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Solution Overview
Problem
In computer systems, the difference in power-up times between core logic and I/O logic supply voltages can lead to undefined control signals being inadvertently driven onto buses, causing memory devices to enter an inoperable state, with existing solutions either requiring additional circuitry or external components that increase complexity and cost.
Innovation Solution
An internal voltage supply sense circuit monitors the core logic supply voltage and generates signals to maintain I/O pads in a high impedance state until the core logic supply voltage reaches a predetermined level, preventing undefined control signals from being driven onto the bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If I/O logic supply voltage is ramped up to final level before core logic supply voltage, then I/O pads can drive signals, but undefined control signals may be inadvertently driven onto the bus causing memory devices to enter inoperable state
Solution Approach 1:
The patent applies preliminary action by detecting the power-up state of core logic supply voltage before allowing I/O pads to drive signals. The sense circuit monitors core logic supply voltage and generates a control signal to maintain I/O pads in high-impedance state until core logic supply voltage reaches a predetermined level, preventing undefined control signals from being driven onto the bus during the power-up transition period
2Reliability
If external components or additional circuitry are used to ensure proper power sequence, then signal integrity is maintained, but device complexity and cost increase
Solution Approach 1:
The patent merges the power sequence control function into the existing I/O logic circuitry. The sense circuit is integrated within the I/O logic and shares resources with existing circuit elements, eliminating the need for separate external power sequence control components while maintaining reliable power sequencing
Solution Approach 2:
The I/O logic performs self-service by internally monitoring its own power-up state through the sense circuit and automatically controlling its output drivers. The I/O logic generates the control signal based on core logic supply voltage detection and uses this signal to manage its own high-impedance state, eliminating dependency on external control components
Data Source
AI summary
Techniques and circuits for ensuring undefined control signals are not inadvertently driven onto a bus due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals to be driven on I/O pads. The sense circuit may generate one or more control signals used to keep I/O pads in a high impedance state.