Semiconductor Memory Bus Voltage Control for Power Reduction
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing power consumption and improving operational reliability due to high data bus voltage amplitudes, which lead to increased charging and discharging demands, especially in three-dimensional stacked NAND flash memories.
Innovation Solution
The implementation of a data bus voltage amplification method using voltages lower than the power source voltage, specifically Vclh−Vt, to reduce power consumption and prevent transistor malfunction, while maintaining stability through controlled gate electric potentials for transistors charging the bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high data bus voltage amplitudes are used for data transmission, then data transmission capability is improved, but power consumption increases due to increased charging and discharging demands
Solution Approach 1:
The patent changes the voltage parameter by introducing a boosted voltage level (Vclh−Vt) that is higher than the standard power source voltage. This voltage boosting is achieved through a dedicated circuit that generates the elevated voltage temporarily during data transmission periods, allowing high-speed data transmission while maintaining lower average power consumption by confining the high voltage to specific time windows rather than continuous operation
Solution Approach 2:
The patent implements periodic action by applying the boosted voltage Vclh−Vt only during specific data transmission periods rather than continuously. The voltage is activated when data needs to be transmitted on the data bus and deactivated during non-transmission periods, creating a periodic pattern that reduces overall power consumption while maintaining transmission capability when needed
2Speed
If high data bus voltage amplitudes are used for data transmission, then data transmission capability is improved, but operational reliability deteriorates due to transistor malfunction risks
Solution Approach 1:
The patent carefully controls the voltage parameter by using a precisely defined boosted voltage level (Vclh−Vt) that is higher than standard voltage for improved transmission, but capped at a safe threshold to prevent transistor breakdown. The voltage is applied only momentarily during data transitions rather than sustained, reducing cumulative stress on transistor components
Solution Approach 2:
The patent applies preliminary action by pre-charging the data bus to the boosted voltage level Vclh−Vt before actual data transmission begins. This preparatory voltage application ensures that when data transitions occur, the bus is already at the optimal voltage level, enabling faster and more reliable transmission while minimizing the duration that transistors are exposed to high voltage stress
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by half to a quarter of previous levels, enhances operational stability, and improves reliability by minimizing data bus charging and discharging, particularly in three-dimensional stacked NAND flash memory configurations.
Implementation Method 1
the third transistor is switched on by applying a first voltage lower than a power source voltage of the first and second latch circuits to a gate of the third transistor to precharge the bus to an electric potential lower than the power supply voltage
Data Source
AI summary
A semiconductor memory device includes a sense amplifier, and the sense amplifier includes a bus, first and second latch circuits, and a third transistor. The first latch circuit includes a first transistor connected to the bus, and the second latch circuit includes a second transistor connected to the bus. When data is transmitted from the first latch circuit to the second latch circuit, a third transistor is switched on to precharge the bus by applying a first voltage that is lower than a power source voltage of the first and second latch circuits to a gate of the third transistor. Thereafter, second and third voltages that are lower than the power source voltage are applied to gates of first and second transistors, respectively.