Memory Bus ZQ Calibration Using Integrated Current Sources
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Solution Overview
Problem
In semiconductor memory systems, the limited number of external pins and absence of external reference calibration devices lead to prolonged calibration times and inadequate periodic calibration, especially as the number of memory devices increases, due to impedance mismatch issues caused by temperature changes.
Innovation Solution
The implementation of a terminal calibration circuit with a pull-down and/or pull-up circuit, along with a reference calibration circuit that generates a calibration current, allowing for concurrent ZQ calibration across multiple memory devices without the need for external ZQ resistors, thereby reducing calibration time and ensuring impedance matching across data buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple memory devices share a single external reference calibration device via external pins, then the number of external pins is reduced, but the calibration time increases significantly
Solution Approach 1:
The patent extracts the reference calibration device from external location to internal integration on the same semiconductor die. Each memory device includes its own reference calibration device (first reference calibration device, second reference calibration device) eliminating the need to share external pins. This allows concurrent calibration of multiple memory devices without time multiplexing, directly resolving the contradiction between pin reduction and calibration time.
Solution Approach 2:
The patent segments the calibration function by providing separate reference calibration devices for different calibration purposes (first for pull-down circuit, second for pull-up circuit). This segmentation enables independent and concurrent calibration operations, further reducing total calibration time while maintaining accurate impedance matching without requiring additional external pins.
2Device complexity
If external reference calibration devices are not provided, then device complexity is reduced, but impedance matching accuracy deteriorates due to temperature changes
Solution Approach 1:
The patent merges the reference calibration device with the memory device by integrating both on the same semiconductor die. This co-location ensures that the reference calibration device experiences identical temperature conditions as the termination component, eliminating temperature-induced impedance mismatches that would occur with external reference devices. The merging approach maintains measurement precision while reducing overall system complexity.
Solution Approach 2:
The patent implements local quality by providing dedicated reference calibration devices specific to each memory device's termination requirements. The first reference calibration device calibrates the pull-down circuit while the second reference calibration device calibrates the pull-up circuit, ensuring locally optimized impedance matching that adapts to local temperature and electrical conditions without requiring external devices.
3Measurement precision
If sequential calibration is used for multiple memory devices, then calibration accuracy is maintained, but productivity decreases
Solution Approach 1:
The patent segments the calibration function into independent parallel paths by providing separate reference calibration devices for each memory device. Each memory device can perform its calibration operations independently using its own reference calibration device, enabling simultaneous calibration of multiple devices. This segmentation maintains calibration accuracy for each device while dramatically increasing overall calibration throughput compared to sequential approaches.
Solution Approach 2:
The patent implements preliminary action by pre-integrating reference calibration devices on each memory device during manufacturing. This preliminary integration prepares each device for independent calibration operations, eliminating the need for time-consuming sequential calibration processes. Multiple devices can undergo calibration simultaneously, improving productivity while maintaining the accuracy that would otherwise require sequential processing.
Data Source
AI summary
A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.