Semiconductor Memory Bypass Control for Mode Conversion
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Solution Overview
Problem
Conventional semiconductor memory devices face data coherency issues and require time to identify modes during conversions between synchronous and asynchronous operations, leading to potential data value changes and dummy cycle times.
Innovation Solution
A semiconductor memory device with a bypass control unit that enables late write and bypass operations in one mode and disables them in another, using mode conversion signals generated by clock signal toggling to maintain data coherency and prevent dummy cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PSRAM devices perform mode conversion between synchronous and asynchronous modes, then the device can operate in both modes, but data coherency problems occur when addresses match between modes
Solution Approach 1:
The patent applies preliminary action by performing address comparison between asynchronous and synchronous modes before mode conversion occurs. The bypass control unit compares the asynchronous address with the synchronous address in advance, and when they match, it generates a bypass signal to prevent the synchronous write operation, thereby preventing data coherency issues before they can occur.
2Adaptability or versatility
If conventional PSRAM devices identify mode conversion, then the device can switch between modes, but dummy cycle time is generated during identification
Solution Approach 1:
The patent applies continuity of useful action by generating the mode conversion signal continuously based on clock signal toggling rather than requiring separate identification cycles. The bypass control unit uses the clock signal's rising and falling edges to automatically generate mode conversion signals, ensuring continuous and seamless mode switching without introducing dummy cycle times.
3Ease of operation
If late write operation is enabled in asynchronous mode, then data can be written to memory cells, but data coherency may change when mode conversion occurs
Solution Approach 1:
The patent applies feedback by using the address comparison result as feedback to control the bypass operation. When the asynchronous address matches the synchronous address, the bypass control unit receives feedback through the comparison unit and generates a bypass signal to prevent the synchronous write, thereby maintaining data coherency while allowing late write operations to function.
Data Source
AI summary
A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.