Memory Data Output Circuit for Bypassed Special Read Access
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Solution Overview
Problem
Existing semiconductor memory devices, such as SDRAMs, experience increased power consumption and operation duration during special read operations, which are 'indifferent' to the presence of normal data, as they still perform data access operations like word line enable and bit line precharge.
Innovation Solution
A semiconductor memory device with a memory cell array, a multi-purpose register for storing data patterns, and an output control circuit that blocks access to the memory cell during special read operations, allowing data patterns to be output without accessing the memory cell, thereby reducing power consumption and operation duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory cell is accessed during special read operations, then data patterns can be read, but power consumption and operation duration increase
Solution Approach 1:
The patent segments the read operation into two distinct types: normal read operations that access the memory cell array, and special read operations that read data patterns from a separate storage unit without accessing the memory cell array. This segmentation allows the system to optimize power consumption by avoiding unnecessary memory cell access during special read operations while maintaining the capability to perform both types of reads.
Solution Approach 2:
The patent introduces an intermediary storage unit that stores data patterns independently from the main memory cell array. This intermediary structure enables special read operations to retrieve data patterns without triggering power-intensive memory cell access operations, thus reducing power consumption while still providing data output functionality.
2Reliability
If the memory cell is accessed during special read operations, then data patterns can be read, but operation duration increases
Solution Approach 1:
The patent segments the read operation into two distinct types: normal read operations that access the memory cell array, and special read operations that read data patterns from a separate storage unit without accessing the memory cell array. This segmentation allows the system to optimize operation duration by avoiding unnecessary memory cell access during special read operations while maintaining the capability to perform both types of reads.
Solution Approach 2:
The patent introduces an intermediary storage unit that stores data patterns independently from the main memory cell array. This intermediary structure enables special read operations to retrieve data patterns without triggering time-consuming memory cell access operations, thus reducing operation duration while still providing data output functionality.
3Reliability
If the memory cell is accessed during special read operations, then data patterns can be read, but unnecessary access operations are performed
Solution Approach 1:
The patent segments the read operation into two distinct types: normal read operations that access the memory cell array, and special read operations that read data patterns from a separate storage unit without accessing the memory cell array. This segmentation allows the system to eliminate unnecessary memory cell access operations during special reads, improving operational efficiency while maintaining data pattern output capability.
Solution Approach 2:
The patent introduces an intermediary storage unit that stores data patterns independently from the main memory cell array. This intermediary structure enables special read operations to retrieve data patterns without performing unnecessary memory cell access operations, thus improving productivity by eliminating wasted operations while still providing data output functionality.
Data Source
AI summary
The example semiconductor memory device may include a memory cell, a storage unit configured to store at least one data pattern, a data output circuit configured to output the stored data during a first type of read operation and configured to output the at least one data pattern during a second type of read operation and an output control circuit for controlling the data output circuit such that the memory cell is not accessed during read operations of the second type. A first example method may include storing at least one data pattern in a storage unit, outputting the stored data within the memory cell in response to a first type of read operation and outputting the at least one data pattern in the storage unit in response to a second type of read operation and blocking access to the memory cell during read operations of the second type.