Memory Storage Using Byte-Filling Bits for Error-Coded Access

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Solution Overview

Problem

Complementary memory cells require two physical memory cells per bit, leading to high overhead and inefficient storage, especially when using codes like 3-of-6 or 4-of-8, and existing byte error codes do not effectively manage byte-filling bits for error detection and correction.

Innovation Solution

Implementing byte-filling bits to encode predefined functionalities, such as inversion, validity, overwritability, and readability, and using Reed-Solomon codes for error correction and detection, reducing the number of memory cells needed and enhancing error management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complementary memory cells are used to store data bits, then reliability of data storage is improved, but memory cell overhead increases to 100%

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidmemory cell overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines multiple functions into the byte-filling bits: they serve as both padding to complete bytes and as encoding carriers for data manipulation instructions (inversion, validity, overwritability, readability). This merging eliminates the need for separate overhead structures while maintaining reliability improvements from complementary memory cells.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The byte-filling bits are designed to perform multiple functions simultaneously: padding incomplete bytes, encoding data manipulation instructions, and participating in error detection/correction schemes. This multi-functionality reduces the need for dedicated overhead bits while improving storage efficiency and reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If x/2-of-x codes are used with complementary memory cells, then memory overhead is reduced to 50-33%, but byte-filling bits are created that require additional management

Engineering Contradiction:
Improvememory overheadVSAvoidbyte management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The byte-filling bits automatically encode the necessary data manipulation instructions based on the stored data patterns. The system uses the existing byte-filling bits to self-manage the data manipulation requirements without needing external control logic, thereby reducing management complexity while maintaining reduced overhead benefits.

Inventive Principle:
Principle #25Self-service

3Productivity

If byte-filling bits are used to encode predefined functionalities, then storage efficiency is improved, but error detection and correction requirements increase

Engineering Contradiction:
Improvestorage efficiencyVSAvoiderror detection and correction requirements
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent incorporates error detection and correction capabilities directly into the byte-filling bit encoding scheme before data storage. By pre-encoding validity information and integrating it with Reed-Solomon error correction codes, the system prepares error handling mechanisms in advance, allowing efficient error detection and correction without compromising storage efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12608269B2Method for memory storage and access
Publication Date: 2026.04.21 INFINEON TECHNOLOGIES AG
  • US12608269B2 patent drawing

AI summary

A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.