Memory Byte-Lane Timing Margin Testing with Parallel Failure Screening
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Solution Overview
Problem
Memory devices experience timing margin degradation over time due to factors like frequency, temperature, and aging, leading to errors and system instability, necessitating efficient testing methods to ensure compliance with timing requirements.
Innovation Solution
A system for parallel timing margin testing across multiple byte lanes of a memory device, involving parallel data streaming and iterative memory tests with varying margin delays to identify failing byte lanes and determine their optimal timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential timing margin testing is performed on each byte lane individually, then testing accuracy is maintained, but testing time and productivity are significantly increased
Solution Approach 1:
The patent segments the timing margin testing process into two distinct phases: (1) a parallel screening phase where multiple byte lanes are tested simultaneously to identify potentially failing lanes, and (2) a sequential verification phase where only the identified failing lanes undergo detailed timing margin measurement. This segmentation allows the system to maintain measurement accuracy for critical failures while dramatically improving overall testing productivity through parallel processing of the initial screening.
Solution Approach 2:
The patent applies different testing quality levels to different byte lanes based on their test results. Byte lanes that pass the parallel screening undergo no further testing (local quality = pass), while only the subset of byte lanes that fail the screening receive the more resource-intensive sequential timing margin measurement (local quality = detailed analysis). This local quality approach optimizes resource allocation by applying high-precision measurement only where necessary.
2Productivity
If parallel memory testing is performed on multiple byte lanes simultaneously, then productivity is improved, but device complexity and test control difficulty increase
Solution Approach 1:
The patent segments the testing architecture into distinct functional blocks: a parallel test execution unit that handles multiple byte lanes simultaneously, a result analysis unit that identifies failing lanes, and a sequential test unit that performs detailed measurements on specific lanes. This segmentation of the test system itself reduces complexity by creating modular, independently controllable units rather than requiring a single complex parallel testing apparatus.
Solution Approach 2:
The patent introduces an intermediary result analysis step between the parallel screening phase and the sequential verification phase. This intermediary unit processes the parallel test results, identifies which byte lanes require further testing, and directs the sequential test resources accordingly. This intermediary layer simplifies the overall system by decoupling the parallel execution complexity from the detailed measurement complexity, allowing each to be optimized independently.
3Measurement precision
If iterative memory tests with varying margin delays are performed, then timing margin determination accuracy is improved, but testing time increases
Solution Approach 1:
The patent performs a preliminary parallel screening test on all byte lanes before conducting iterative timing margin tests. This preliminary action identifies the specific byte lanes that require detailed timing margin analysis, allowing the iterative tests with varying margin delays to be applied only to a small subset of failing lanes rather than all lanes. This dramatically reduces the total testing time while maintaining accurate timing margin determination for the critical failing lanes.
Solution Approach 2:
The patent changes the test parameters (margin delays) iteratively only for the byte lanes that fail the initial screening, rather than applying parameter changes to all byte lanes. By concentrating the iterative parameter variation on a small subset of failing lanes, the patent achieves accurate timing margin determination for problematic lanes while minimizing the overall testing duration.
Data Source
AI summary
The present disclosure describes systems and methods for determining timing margins in parallel for a plurality of byte lanes coupling a memory device to a memory controller circuit. Memory testing can be performed on multiple byte lanes in parallel to detect a memory test failure event for one or more failing byte lanes. In response to detecting the memory test failure event for the one or more failing byte lanes, a timing margin for the one or more failing byte lanes can be determined. Additional memory testing can be performed to determine the timing margins for the remaining byte lanes while calibrated state signals are provided to the byte lanes with already determined timing margins.