Memory CA Parity Signaling Using Shared Data Pins
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Solution Overview
Problem
Existing memory systems face challenges in performing parity checking on command/address (CA) pins due to constraints on the number of pins available and varying timing requirements across different applications.
Innovation Solution
The memory device uses cycles of data-associated pins such as data mask/invert (DMI), error correction code (ECC), or redundant data strobe (RDQS) to convey CA parity information, even when a dedicated pin is not available.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated CA parity pin is used, then parity checking reliability is improved, but the number of pins required increases
Solution Approach 1:
The patent applies multi-functionality by enabling data-associated pins (DMI, ECC, RDQS) to serve dual purposes: their primary data transfer function and an additional function of conveying CA parity information. This eliminates the need for a dedicated parity pin while maintaining reliability, as the same pins are reused for multiple purposes at different time intervals.
2Adaptability or versatility
If data-associated pins are used for parity checking, then pin configuration flexibility is improved, but timing complexity increases
Solution Approach 1:
The patent segments the timing intervals into distinct phases where data-associated pins are allocated for either data transfer or parity conveyance. By dividing the communication timeline into separate intervals, the system manages timing complexity through structured segmentation rather than simultaneous multi-function operation, making the control logic more manageable.
Solution Approach 2:
The patent employs periodic action by alternating between data transfer cycles and parity checking cycles on the same pins. The data-associated pins periodically switch between their primary data function and the secondary parity function in a rhythmic, predictable pattern, which simplifies timing control compared to asynchronous or simultaneous operations.
3Quantity of substance
If dedicated CA parity pin is not used, then pin count is reduced, but timing constraints become more restrictive
Solution Approach 1:
The patent applies preliminary action by performing parity checking operations during idle intervals or unused time slots within the existing data transfer timeline. Rather than adding time overhead, the system proactively utilizes previously underutilized time resources to convey parity information, thereby avoiding additional timing constraints while reducing pin count.
Data Source
AI summary
Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.