Multi-Plane Memory Cache Latch Initialization
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Solution Overview
Problem
Current memory devices face inefficiencies in program operation speed due to the sequential initialization of cache latches during multi-plane programming, leading to increased program times and potential data errors.
Innovation Solution
Implementing a memory device with page buffer groups and control logic that simultaneously initialize cache latches across multiple planes in response to a multi-plane program command, allowing for concurrent data storage across multiple planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache latches are initialized sequentially during multi-plane programming, then the initialization process is simple to control, but the program operation speed decreases and total program time increases
Solution Approach 1:
The cache latch initialization process is segmented by plane, with each plane's cache latches being initialized independently and simultaneously through plane-specific control signals. This allows parallel initialization across multiple planes while maintaining organized control over each segment.
Solution Approach 2:
Cache latches are initialized before data is written to them during the multi-plane program operation. The control logic prepares the cache latches in advance by setting them to a known initial state, ensuring they are ready to receive data immediately when the program operation begins.
2Loss of time
If cache latches are initialized sequentially, then the control logic remains simple, but the total program time increases
Solution Approach 1:
The initialization operations for cache latches across multiple planes are merged into a single concurrent operation. The control logic issues initialization signals to multiple planes simultaneously, combining what would otherwise be separate sequential operations into one unified parallel process.
Solution Approach 2:
The control logic dynamically adapts its behavior based on the multi-plane program command, transitioning from sequential to parallel initialization mode. It actively manages multiple initialization operations concurrently, adjusting control signals according to which planes are being programmed.
3Productivity
If sequential initialization is used, then the risk of control errors is low, but program operation efficiency decreases
Solution Approach 1:
The control logic monitors the initialization status of cache latches across multiple planes and adjusts control signals accordingly. It receives feedback about which planes are being programmed and ensures each plane's cache latches are properly initialized before data writing begins, maintaining data accuracy while improving efficiency.
Data Source
AI summary
A memory device includes: a plurality of memory cells grouped into a plurality of planes; page buffer groups corresponding to respective ones of the plurality of planes, the page buffer groups including a plurality of page buffer circuits, each of the plurality of page buffer circuits including cache latches which are configured to receive data to be stored in memory cells in the plurality of planes; and control logic for controlling the page buffer groups to simultaneously initialize cache latches corresponding to at least two planes, among the cache latches, in response to a multi-plane program command, wherein the multi-plane program command instructs a multi-plane program operation of simultaneously storing data in plural planes among the plurality of planes.