Memory Page Programming with Cache Latches and Data Recovery
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Solution Overview
Problem
In non-volatile memory devices, programming multiple data pages into the memory cell array is inefficient as it requires waiting for the completion of each page before starting the next, leading to inefficient data writing and potential loss of data if a page fails to program successfully.
Innovation Solution
Implementing a cache program method where page data is stored in a cache latch and a data latch, allowing simultaneous programming of multiple pages without waiting for previous pages to complete, with mechanisms for data recovery if a page fails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one page data is programmed at a time in sequential order, then programming accuracy is ensured, but programming speed and productivity deteriorate due to waiting time between pages
Solution Approach 1:
The patent stores multiple pages of data in advance in cache latches (CL0-CL3) and data latches (DL0-DL3) before programming begins. This preliminary storage allows the programming operation to proceed continuously through multiple pages without waiting for external data input, thereby improving programming speed while maintaining data integrity through verified storage mechanisms.
Solution Approach 2:
The patent introduces latch circuits (cache latches and data latches) as intermediary storage elements between the external interface and the memory cell array. These latches act as buffers that decouple the programming speed from the data input speed, allowing continuous programming operations while ensuring data accuracy through controlled data transfer and verification processes.
2Productivity
If multiple pages are programmed simultaneously using cache and data latches, then programming efficiency improves, but device complexity increases due to additional latch circuits
Solution Approach 1:
The patent divides the data storage function into multiple segmented latch circuits (cache latches CL0-CL3 and data latches DL0-DL3), where each latch handles specific page data. This segmentation allows parallel preparation of multiple pages while keeping each individual latch circuit relatively simple, thereby achieving continuous programming capability without excessive complexity in any single component.
Solution Approach 2:
The latch circuits in the patent serve multiple functions: they act as temporary storage buffers, data transfer intermediaries, and verification points. By making these circuits multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby improving programming efficiency while controlling overall device complexity through versatile component design.
Data Source
AI summary
A memory device, memory system, and a method of operating the same are provided. The method for operating the memory device, includes storing first page data in a cache latch, storing the first page data in a first data latch and storing last page data in a second data latch, programming memory cells of a first page of a memory array with the first page data, storing the first page data in the second data latch and storing second page data in the first data latch, and programming memory cells of a second page with a second page data.