Semiconductor Memory Cache Read Voltage Sequencing

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Solution Overview

Problem

Semiconductor memory devices face challenges in accurately reading multi-bit data due to overlapping threshold voltage distributions, leading to potential errors in data retrieval.

Innovation Solution

A semiconductor memory device and method that utilize a cache read method, employing multiple read voltages to determine whether a memory cell's threshold voltage falls within a specific range, reducing read time by sequentially supplying read voltages to a word line and sensing bit line voltages to differentiate between normal and over-sampling data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple read voltages are sequentially supplied to read data, then data retrieval accuracy is improved, but read time increases

Engineering Contradiction:
Improvedata retrieval accuracyVSAvoidread time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by reading out data using a first read voltage before actually needing the data for final output. This pre-reading allows the system to prepare data in advance and use it for error correction, thereby reducing the overall read time when the data is finally needed for output.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by making the read voltage variable rather than fixed. The controller dynamically selects between a first read voltage (for normal data reading) and a second read voltage (for over-sampling data reading based on threshold voltage distribution), optimizing the reading process adaptively to reduce time while maintaining accuracy.

Inventive Principle:
Principle #15Dynamics

2Reliability

If over-sampling data is read using multiple voltages, then error correction capability is improved, but device complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by making the page buffer handle multiple functions through a single structure. The same page buffer that normally just reads and stores data is also used to perform error correction processing by storing over-sampling data and comparing it with normal read data, thereby eliminating the need for separate error correction circuitry.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements self-service by having the page buffer perform error correction functions using its own stored data. The page buffer compares over-sampling data (read at different voltages) with normal read data to determine threshold voltage distributions and correct errors, without requiring external error correction circuits.

Inventive Principle:
Principle #25Self-service

3Productivity

If threshold voltage distributions are narrow, then memory cell integration is improved, but data reading accuracy deteriorates

Engineering Contradiction:
Improvememory cell integrationVSAvoiddata reading accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies partial action by reading data at specific voltage points (first read voltage and second read voltage separated by a specific level) rather than continuously scanning all possible voltages. This targeted approach provides sufficient information about threshold voltage distribution to maintain accuracy while reducing the complexity of the reading process.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8902674B2Semiconductor memory device and method of reading out the same
Publication Date: 2014.12.02 SK HYNIX INC
  • US8902674B2 patent drawing
  • US8902674B2 patent drawing
  • US8902674B2 patent drawing

AI summary

A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.