Non-volatile Memory Cache Register Noise Reduction
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Solution Overview
Problem
The reliability of cache program operations in non-volatile memory devices is compromised due to power voltage noise generated during the clearing of cache registers, which can lead to unintended programming and reduced reliability.
Innovation Solution
A method and device where data is stored in a cache register, moved to a main register, and then the cache register is cleared before programming, ensuring that the cache register is only cleared during the initial page program, thereby preventing power voltage noise and maintaining programming reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the cache register is cleared during programming operation to prepare for next page, then the cache register is ready for new data, but power voltage noise is generated which reduces programming reliability
Solution Approach 1:
The patent segments the register clearing operation into two distinct phases: (1) clearing the cache register after data transfer to main register, and (2) conditionally clearing the main register only for the initial page program. This segmentation isolates the noise-generating clearing operation from the critical programming phase, allowing cache register preparation without interfering with subsequent programming reliability.
Solution Approach 2:
The patent performs the cache register clearing action in advance, immediately after data is transferred to the main register and before the programming operation begins. By completing the clearing operation preliminarily, the cache register is prepared for the next page while the programming operation proceeds without noise interference, as the clearing has already been completed in the previous cycle.
2Productivity
If the cache register is cleared during sensing section, then the register is prepared for next operation, but noise is generated that decreases operation reliability
Solution Approach 1:
The patent extracts the harmful clearing operation from the sensing section and relocates it to occur after the programming operation completes. By taking out the clearing action from the critical sensing and programming phases, the patent eliminates noise generation during these operations while maintaining operational throughput, as the clearing occurs in the safe zone after programming is complete.
3Reliability
If data is moved from cache register to main register and then cache register is cleared, then unintended programming is prevented, but power voltage noise is still generated
Solution Approach 1:
The patent applies different clearing strategies to different registers based on their specific functions: the cache register is cleared after each data transfer to prevent unintended programming, while the main register is cleared only for the initial page program. This local differentiation ensures that clearing operations occur only where necessary for data integrity, minimizing noise generation while maintaining programming accuracy.
Data Source
AI summary
A non-volatile memory device having a memory array is configured to prevent power voltage noise generation during programming, thereby improving reliability. An associated programming method of the non-volatile memory device includes storing data input from an external source to a cache register. The stored data is moved to a main register. The cache register is cleared and the data stored in the main register is programmed to the memory cell array.