Memory Cache Synchronization via Sequential Identifiers

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Memory systems face reliability issues and increased latency during asynchronous power losses, where invalid data can be written to the cache, leading to system failures, and existing solutions to improve reliability by writing data to non-volatile memory can impact performance.

Innovation Solution

Implementing a cache synchronization method that assigns sequential identifiers to data written to non-volatile memory, allowing the system to recover valid data quickly after a power loss by copying it back to the cache, thereby reducing latency and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is written to non-volatile memory to improve reliability during power loss, then system reliability is improved, but write latency increases

Engineering Contradiction:
Improvedata integrityVSAvoidwrite latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by assigning sequential identifiers to data before power loss occurs and storing metadata about the write state. After power restoration, the controller uses these pre-assigned identifiers to quickly determine which data needs recovery without re-writing all data, thus reducing post-power-loss recovery time while maintaining data integrity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments data into individual write commands with unique sequential identifiers. This segmentation allows the system to track and recover only the specific data segments that were not properly written during power loss, rather than treating the entire cache as a single unit that needs full synchronization, thereby reducing recovery latency

Inventive Principle:
Principle #1Segmentation

2Reliability

If cache synchronization is performed after power loss to recover valid data, then data integrity is improved, but system latency increases

Engineering Contradiction:
Improvedata validityVSAvoidrecovery latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system implements feedback by continuously tracking the state of data writes using sequential identifiers and metadata. After power loss, the controller receives feedback about which identifiers correspond to validly written data versus invalid data, enabling selective recovery only of necessary data segments, thus minimizing recovery latency while ensuring data validity

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Sequential identifiers are assigned to data in advance before power loss occurs. This preliminary action creates a roadmap that enables the system to quickly identify and recover only the specific data that needs restoration after power loss, rather than performing blanket cache synchronization, thereby reducing recovery time

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240272806A1Memory device cache synchronization
Publication Date: 2024.08.15 MICRON TECHNOLOGY INC
  • US20240272806A1 patent drawing
  • US20240272806A1 patent drawing
  • US20240272806A1 patent drawing

AI summary

Methods, systems, and devices for memory device cache synchronization are described. Some implementations may synchronize a cache after a power loss event. For example, during normal operation, a memory system may move data from a cache to a non-volatile memory. Each data may be assigned a sequential identifier when being moved. After a power loss event, the memory system may determine which data has been moved to the non-volatile memory (e.g., based on the identifiers) and may assume that data associated with the identifiers stored to the non-volatile memory is valid, whereas data associated with other identifiers not present in the non-volatile memory is invalid. The memory system may then recover the valid data by copying the valid data to the cache.