Memory Cache Management via Tiered Compaction Blocks
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Solution Overview
Problem
Conventional memory sub-systems face inefficiencies due to significant resource consumption and increased latency caused by frequent copying of memory pages between cache and data compaction blocks, leading to reduced system efficiency and increased latency.
Innovation Solution
Implementing a tiered set of data compaction blocks to facilitate caching, where SLC blocks are allocated based on modification frequency, reducing the need for frequent copying and optimizing space allocation between write blocks and data compaction blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory pages are frequently copied between cache and data compaction blocks, then data integrity is maintained, but resource consumption increases and latency is reduced
Solution Approach 1:
The patent segments the memory sub-system into distinct blocks (cache blocks, data compaction blocks, write blocks) and implements a tiered structure where memory pages are organized by modification frequency. This segmentation allows the system to handle different types of data in different locations, reducing the need for frequent copying while maintaining data integrity.
Solution Approach 2:
The patent implements dynamic block allocation and memory page migration based on modification frequency. Blocks are dynamically assigned as cache blocks or data compaction blocks, and memory pages are moved between blocks based on their access patterns. This dynamic adaptation reduces unnecessary copying operations while ensuring data integrity is maintained through controlled migration.
2Quantity of substance
If more space is allocated for low-bit density caching, then caching capacity increases, but the amount of space available for host space decreases
Solution Approach 1:
The patent implements dynamic block allocation where blocks can be reassigned between cache and host space based on system needs and modification frequency patterns. This dynamic allocation allows the system to optimize the balance between caching capacity and host space availability, ensuring both functions can operate efficiently without excessive static allocation.
Solution Approach 2:
The patent applies different allocation strategies to different regions of the memory sub-system based on local requirements. Cache blocks are allocated with specific characteristics for frequent access, while data compaction blocks and host space are allocated differently. This local differentiation allows optimal use of space without uniformly sacrificing host space for caching capacity.
3Reliability
If memory pages are copied frequently between blocks, then data synchronization is maintained, but latency increases
Solution Approach 1:
The patent segments memory pages into different categories based on modification frequency and locations them in appropriate blocks. This segmentation reduces the frequency of copying operations by placing frequently modified pages in cache blocks and less frequently modified pages in data compaction blocks, thereby reducing latency while maintaining synchronization through targeted copying only when necessary.
Solution Approach 2:
The patent performs preliminary classification and placement of memory pages based on their modification frequency before copying operations are needed. By pre-organizing pages in appropriate blocks based on their access patterns, the system reduces the need for frequent copying and minimizes latency while maintaining data synchronization.
Data Source
AI summary
A first data item is programmed to a first memory page of a first block included in a cache that resides in a first portion of a memory device. The first data item is associated with a first processing thread. A second memory page including a second data item associated with the first processing thread is identified. The second memory page is contained by a second block of the cache. The first data item and the second data item are copied to a second portion of the memory device. The first memory page and each of the one or more second memory pages are designated as invalid.