Memory System Caching Mapping Information Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing memory systems with non-volatile NAND type flash memory face inefficiencies in address translation due to slow access speeds, leading to increased processing time for address translation information retrieval, which is mitigated by using a cache memory but requires balancing cache capacity and performance.
Innovation Solution
A memory system configuration that efficiently caches address translation information by managing cache data in segments within a dynamic random access memory (DRAM), allowing multiple pieces of mapping information to be stored without gaps, thereby increasing the amount of cached information while reducing DRAM capacity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address translation information is stored in non-volatile memory, then data persistence is achieved, but access speed is slow and processing time increases
Solution Approach 1:
The patent segments address translation information into multiple LUT segments that can be selectively cached in DRAM. By dividing the complete address translation table into manageable segments, the system can load only frequently accessed segments into high-speed DRAM memory, achieving fast access for common operations while maintaining the complete address translation capability in non-volatile memory for persistence.
Solution Approach 2:
The patent introduces DRAM cache memory as an intermediary between the host and non-volatile memory for storing LUT segments. This intermediary layer provides high-speed access to address translation information while the non-volatile memory maintains the complete address translation data, resolving the speed-persistence contradiction.
2Productivity
If DRAM capacity is increased to cache more address translation information, then cache hit rate improves, but cost and memory resource consumption increase
Solution Approach 1:
By segmenting the LUT into multiple smaller segments, the system can efficiently utilize limited DRAM capacity to cache the most frequently accessed address translation segments. This segmentation allows for selective caching strategies that maximize cache hit rates without requiring large amounts of DRAM.
Solution Approach 2:
The patent dynamically manages LUT segments in DRAM based on access patterns and system conditions. By changing the caching parameters (which segments are cached, when they are updated, and how they are managed), the system optimizes cache performance within the constraints of available DRAM capacity.
Data Source
AI summary
A memory system is configured to be connected to a host. The memory system includes a non-volatile first memory, a second memory, and a controller configured to manage cache data stored in the second memory in units of a segment such that each segment includes a plurality of pieces of the cache data. Each of the plurality of pieces of the cache data includes mapping information which correlates a logical address value indicating a location in a logical address space provided by the memory system to the host with a location in the first memory. At least two pieces of the cache data are arranged in one segment without a space therebetween.