Multi-Rank Memory Controller Calibration Without Bus Blocking
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Solution Overview
Problem
In multi-rank memory systems, calibration operations for signaling interfaces tie up an entire data bus, blocking data access to memory devices in other ranks that are not being calibrated, leading to performance degradation.
Innovation Solution
A memory controller calibrates parameters for data transmission on one data bus while simultaneously transferring data with a memory device in another rank via a different data bus, allowing calibration to occur without completely blocking data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibration operations are performed on signaling interfaces in multi-rank memory systems, then signaling accuracy is improved, but data bus availability for other ranks deteriorates
Solution Approach 1:
The patent divides the data bus into multiple separate data buses, with each data bus dedicated to a specific memory rank. This segmentation allows calibration operations on one data bus to proceed without blocking data access to other data buses, thereby maintaining both signaling accuracy and overall data bus availability across the multi-rank memory system.
2Reliability
If calibration operations are performed on one rank, then signaling interface performance is improved, but access to other ranks is blocked
Solution Approach 1:
By segmenting the shared data bus into multiple dedicated data buses (one per memory rank), the patent enables parallel operation where calibration on one data bus does not prevent simultaneous data access to other data buses. This eliminates the time loss for accessing other ranks during calibration operations.
Solution Approach 2:
The patent enables continuous data access to memory ranks that are not undergoing calibration by providing dedicated data buses for each rank. While one data bus is occupied with calibration, other data buses continue to facilitate uninterrupted data access to their respective memory ranks, maintaining continuous useful action across the system.
Data Source
AI summary
A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.