Integrated Memory Assembly Calibration via Control Die
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Solution Overview
Problem
The slow calibration process of non-volatile semiconductor storage devices is inefficient due to the need for external testing, which increases production costs and time, as it involves transferring data through a narrow interface using a slow protocol.
Innovation Solution
The integration of a control die with the memory die allows for local calibration and testing, optimizing operational parameters and reducing calibration time by using a wide interface for faster data transfer and parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If calibration is done using external testing equipment with narrow interface, then manufacturing precision can be maintained, but calibration time increases significantly
Solution Approach 1:
The calibration function is extracted from external testing equipment and integrated directly into the memory die through dedicated calibration circuitry. This allows calibration operations to be performed internally without requiring data transfer through narrow external interfaces, thereby maintaining calibration accuracy while dramatically reducing calibration time.
Solution Approach 2:
A wide interface is introduced as an intermediary between the memory die and external testing equipment, enabling high-speed data transfer during calibration operations. This wide interface acts as a mediator that preserves calibration precision while overcoming the speed limitation of traditional narrow interfaces.
2Reliability
If calibration is performed at wafer level with external equipment, then comprehensive testing can be conducted, but production costs increase
Solution Approach 1:
The memory die is equipped with self-calibration capabilities through integrated calibration circuitry that can perform comprehensive testing and calibration operations autonomously. This self-service approach eliminates the need for expensive external testing equipment while maintaining thorough testing coverage, thereby reducing production costs without compromising reliability.
Solution Approach 2:
The calibration and testing functions are merged with the memory die structure itself, combining what were previously separate external testing operations with the internal memory architecture. This integration allows comprehensive reliability testing to be performed as part of the manufacturing process without requiring additional external equipment or steps.
3Device complexity
If data is transferred through narrow interface using slow protocol, then device complexity is reduced, but calibration speed decreases
Solution Approach 1:
The interface bandwidth is expanded by adding more data paths in parallel, transitioning from a narrow single-path interface to a wide multi-path interface. This dimensional expansion of the interface allows high-speed data transfer during calibration operations while keeping each individual data path relatively simple, thus maintaining manageable device complexity.
Data Source
AI summary
An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the calibrated one or more operational parameters.