Memory Calibration Using Predetermined Mask to Reduce Boot Time

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Solution Overview

Problem

The boot time of electronic devices equipped with dynamic random access memory (DRAM) is increased due to time-consuming parameter calibration processes, affecting user experience and making it difficult to ensure normal device operation.

Innovation Solution

A method and system for memory calibration in a system-on-chip (SoC) IC that includes controlling a physical layer circuit to apply power and perform initialization, triggering impedance calibration, and performing data access tests on a predetermined mask to efficiently calibrate memory without unnecessary scanning, thereby reducing boot time and ensuring reliable operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If parameter calibration is performed in subsequent phases to ensure normal operation, then reliability is improved, but boot time increases

Engineering Contradiction:
Improvenormal operationVSAvoidboot time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs impedance calibration during the initialization phase before subsequent calibration operations. A predetermined mask is configured in advance to define a calibration region, and test points are pre-positioned within this region. This preliminary setup enables faster calibration execution in later phases without compromising reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements early termination of calibration operations based on success criteria. When data access tests succeed within the predetermined mask region, subsequent calibration operations are selectively stopped, skipping unnecessary calibration steps. This reduces boot time while ensuring sufficient calibration quality for normal operation.

Inventive Principle:
Principle #21Skipping (Rushing through)

2Reliability

If comprehensive calibration operations are performed to ensure reliable operation, then reliability is improved, but calibration time increases

Engineering Contradiction:
Improvereliable operationVSAvoidcalibration time
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent defines a predetermined mask that identifies a specific calibration region within the data eye diagram. Test points are concentrated within this localized region rather than scanning the entire parameter space. This local focus ensures reliable calibration of critical parameters while reducing overall calibration time by ignoring less critical regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent performs calibration tests on a subset of test points within the predetermined mask region rather than exhaustively testing all possible parameters. The calibration succeeds with partial action (testing only critical points) rather than excessive action (comprehensive scanning), achieving reliable operation with reduced calibration time.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If full scanning calibration is performed, then measurement precision is improved, but productivity decreases

Engineering Contradiction:
Improvecalibration accuracyVSAvoidcalibration efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the calibration process into distinct phases: initialization phase with impedance calibration, and subsequent phases with data access tests using a predetermined mask. This segmentation allows different measurement strategies for different phases, achieving sufficient precision without exhaustive scanning throughout the entire process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent achieves adequate calibration precision by testing only a partial set of points within the predetermined mask region rather than performing full scanning calibration. The selected test points are sufficient to ensure reliable operation while dramatically improving calibration efficiency compared to comprehensive scanning.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11862224B2Method for performing memory calibration, associated system on chip integrated circuit and non-transitory computer-readable medium
Publication Date: 2024.01.02 REALTEK SEMICON CORP
  • US11862224B2 patent drawing
  • US11862224B2 patent drawing
  • US11862224B2 patent drawing

AI summary

A method for performing memory calibration and an associated System on Chip (SoC) Integrated Circuit (IC) are provided. The method may include: in a power-up and initialization phase, controlling a physical layer (PHY) circuit within the SoC IC to apply power to a memory through a pad set and perform initialization on the memory; in an impedance-calibration-related phase, triggering the memory to perform impedance calibration regarding a set of data pins; in at least one subsequent phase, during performing any calibration operation among a reading-related calibration operation and a writing-related calibration operation, performing a data access test corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye; and according to whether the data access test is successful, selectively stopping the any calibration operation.