Memory Controller Calibration Skipping Logic
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Solution Overview
Problem
The frequent changes in power-performance states in computing systems lead to increased power consumption due to the dependency of DRAM calibration on operational clock frequency, as calibration processes are repeated each time the frequency changes, consuming additional power.
Innovation Solution
Implementing a memory controller with timers to skip memory calibration during transitions between power-performance states, thereby preventing unnecessary calibration and reducing power consumption by only calibrating when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory calibration is performed every time the operational clock frequency changes, then the DRAM performance is optimized for each frequency, but the power consumption increases due to frequent calibration processes
Solution Approach 1:
The system performs memory calibration in advance when the frequency actually changes, and skips calibration when transitioning between p-states with the same frequency. The memory controller checks whether calibration is necessary before executing it, performing calibration only when the operational clock frequency changes, thereby avoiding redundant calibration operations while ensuring DRAM performance is optimized when needed
Solution Approach 2:
The invention changes the calibration trigger condition from every p-state transition to only when the operational clock frequency changes. By monitoring the clock frequency parameter rather than simply detecting any p-state change, the system adapts the calibration process to actual performance requirements, reducing unnecessary calibration operations while maintaining optimal DRAM performance
2Adaptability or versatility
If the frequency of changes to power-performance states increases, then the system adapts better to varying workload requirements, but the amount of power consumed by calibration processes increases
Solution Approach 1:
The system changes the calibration trigger parameter from p-state transition events to actual clock frequency changes. This allows the system to maintain high adaptability to varying workload requirements through frequent p-state transitions while reducing energy loss by only performing calibration when the clock frequency actually changes, filtering out redundant calibration operations
Data Source
AI summary
Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.