Memory Device Cap Layer Polishing for Via Protrusion
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Solution Overview
Problem
Current memory device manufacturing processes face challenges in improving wet-etch efficiency and reducing conductive via protrusion, which affects the processing window and manufacturing margin, leading to inconsistent and costly production.
Innovation Solution
The method involves forming a protective cap layer of resistive material over memory devices, followed by polishing to enhance wet-etch efficiency and planarization, allowing for efficient removal of insulative materials and reducing conductive via protrusion, thereby improving manufacturing consistency and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing processes are used without a protective cap layer, then the process is simpler, but wet-etch efficiency is poor and conductive via protrusion occurs
Solution Approach 1:
A protective cap layer of resistive material is formed over the memory device before subsequent processing steps. This preliminary action protects the memory device during manufacturing and enables improved wet-etch efficiency in later steps, resolving the contradiction by preparing the structure in advance to achieve better etching performance.
Solution Approach 2:
The protective cap layer acts as an intermediary element between the memory device and the etching process. It mediates the interaction by providing a controlled interface that improves wet-etch efficiency while protecting the underlying structure, thereby enhancing manufacturing precision without requiring fundamental changes to the overall process.
2Manufacturing precision
If conventional manufacturing processes are used without polishing, then the process is shorter, but conductive via protrusion occurs affecting manufacturing margin
Solution Approach 1:
Polishing is performed on the protective cap layer before forming insulative materials and conductive vias. This preliminary planarization action prevents conductive via protrusion by creating a flat surface in advance, ensuring that subsequent via formation occurs at the correct elevation and improving manufacturing precision without significantly impacting throughput.
3Reliability
If the protective cap layer is not polished, then manufacturing steps are reduced, but processing window is narrowed and consistency is reduced
Solution Approach 1:
The protective cap layer is formed and polished as a preliminary step before depositing insulative materials and forming conductive vias. This advance preparation ensures a controlled and consistent starting point for subsequent processing, narrowing the processing window and improving manufacturing reliability by eliminating variability in surface elevation.
Solution Approach 2:
The surface topology parameter is changed from non-planar to planar through polishing of the protective cap layer. This parameter change creates a consistent surface condition that improves manufacturing reliability and ensures uniform processing in subsequent steps, justifying the additional processing step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the manufacturing margin by improving wet-etch efficiency and reducing conductive via protrusion, resulting in more consistent and cost-effective memory device production with enhanced processing windows.
Implementation Method 1
polishing the cap layer to improve a processing window by improving wet-etch efficiency, lessening conductive via protrusion
Implementation Method 2
improving wet-etch efficiency
Data Source
AI summary
Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.