Semiconductor Memory Cap Layer Thickness Segmentation
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Solution Overview
Problem
The existing one-time programmable (OTP) memory cell structures face limitations in reducing the breakdown voltage of capacitors due to the thickness constraints of the capacitor dielectric layer, which also affects the protection of the metal gate during the high-resistance metal etching process.
Innovation Solution
A semiconductor memory structure is designed with a cap layer having different thicknesses in the transistor and capacitor forming regions, where the cap layer acts as a capacitor dielectric, allowing for a thinner layer in the capacitor region to reduce breakdown voltage while maintaining protection for the metal gate, and additional layers such as titanium nitride or tantalum nitride are used for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitor dielectric layer thickness is reduced, then the breakdown voltage of the capacitor can be reduced, but the protection of the metal gate during high-resistance metal etching process is compromised
Solution Approach 1:
The patent divides the cap layer into two distinct functional layers: a thick cap layer (first cap layer) in the transistor forming region for metal gate protection, and a thin cap layer (second cap layer) in the capacitor forming region that serves as the capacitor dielectric layer. This segmentation allows each layer to have optimized thickness for its specific function, resolving the contradiction between protection and breakdown voltage reduction.
Solution Approach 2:
The patent applies different thicknesses of the cap layer to different regions of the semiconductor structure. The first cap layer has a first thickness (200-300 angstroms) in the transistor forming region for adequate protection, while the second cap layer has a second thickness (20-50 angstroms) in the capacitor forming region to achieve the desired breakdown voltage. This local differentiation allows simultaneous optimization of both protection and electrical performance.
2Reliability
If the capacitor dielectric layer thickness is reduced, then the breakdown voltage can be reduced, but the compatibility with logic technology and non-volatile strength are compromised
Solution Approach 1:
The patent segments the cap layer function into two separate layers with different thicknesses, allowing the capacitor dielectric layer to be thin enough for low breakdown voltage while maintaining the thick cap layer in the transistor region for logic technology compatibility and non-volatile strength.
Solution Approach 2:
The thick cap layer in the transistor forming region serves multiple functions: it protects the metal gate during etching, provides mechanical strength, and maintains compatibility with logic technology. The thin cap layer in the capacitor region provides the necessary dielectric function for low breakdown voltage. This multi-functionality resolves the contradiction between breakdown voltage reduction and technology compatibility.
Data Source
AI summary
A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.