Semiconductor Memory Capacitance Optimization for Readout and Refresh
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The capacitance of the capacitor in semiconductor memory apparatuses is not optimized for both normal readout/write-in and automatic refreshing modes, leading to increased current consumption by the sense amplifier, with the capacitance being either overcharged or undercharged, affecting sensing speed and current consumption.
Innovation Solution
The semiconductor memory apparatus includes a sense amplifier with a first and second power supply intermediate node, switching devices to connect different power supply voltages, and capacitors that satisfy a specific capacitance ratio equation to optimize capacitance for both modes, with additional switching devices and capacitors for parallel voltage application in automatic refreshing mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the capacitance of the capacitor is optimized for normal readout/write-in mode, then the sensing speed is improved, but the current consumption increases in automatic refreshing mode
Solution Approach 1:
The patent applies dynamics by making the capacitance value changeable based on operation mode. A switching device selectively connects different capacitors (first capacitor for normal mode, second capacitor for refreshing mode) to the power supply intermediate node, allowing the circuit to dynamically adjust its electrical characteristics to match different operational requirements, thus achieving both fast sensing and low power consumption in different modes
2Use of energy by moving object
If the capacitance of the capacitor is optimized for automatic refreshing mode, then the current consumption is reduced, but the sensing speed decreases in normal readout/write-in mode
Solution Approach 1:
The patent applies dynamics by making the capacitance value changeable based on operation mode. A switching device selectively connects different capacitors (first capacitor for normal mode, second capacitor for refreshing mode) to the power supply intermediate node, allowing the circuit to dynamically adjust its electrical characteristics to match different operational requirements, thus achieving both fast sensing and low power consumption in different modes
3Device complexity
If a single capacitor value is used for both modes, then the device complexity is reduced, but the performance is suboptimal for at least one mode
Solution Approach 1:
The patent applies segmentation by dividing the capacitor function into multiple independent capacitors (first capacitor and second capacitor with different capacitance values) that can be selectively connected. This segmentation allows each capacitor to be optimized for specific operational modes, with the switching device selecting the appropriate capacitor based on the current mode, thus achieving mode-optimized performance without excessive complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration optimizes the capacitance for overdrive voltage, reducing current consumption by the sense amplifier and maintaining consistent sensing speeds in both modes.
Implementation Method 1
a first capacitor, connected to the overdrive voltage and charging the overdrive voltage
Implementation Method 2
a first switching device, connecting a first power supply voltage acting as an overdrive voltage to the first power supply intermediate node of the sense amplifier when the sense amplifier is driven during a first period
Data Source
AI summary
A semiconductor memory apparatus performs a selection in a normal readout/write-in mode and an automatic refreshing mode and includes a sense amplifier reading out data from a memory device, a first switching device connecting a first power supply voltage acting as an overdrive voltage to a first power supply intermediate node during a first period and then connecting a second power supply voltage acting as an array voltage to the first power supply intermediate node, a second switching device connecting the fourth power supply voltage to a second power supply intermediate node of the sense amplifier when the sense amplifier is driven, a first capacitor connected to the overdrive voltage and charging it, a third switching device switched on in the automatic refreshing mode, and a voltage generator generating a third power supply voltage and applying it and the first power supply voltage in parallel through the third switching device.