Memory Capacitor Contact Layout for Dense DRAM Reliability
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Solution Overview
Problem
The increasing integration level of semiconductor memory devices poses challenges in ensuring reliability due to the reduced design rule for components, particularly the spacing between word lines, which affects the stability and performance of the devices.
Innovation Solution
The semiconductor memory device incorporates specific structural arrangements, including a substrate with defined cell and peripheral areas, capacitor structures, and contact plugs that ensure vertical alignment and equal surface levels, enhancing electrical connections and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration level of semiconductor memory devices is increased, then the number of semiconductor elements in the same area is increased, but the design rule for components decreases and reliability becomes difficult to ensure
Solution Approach 1:
The patent applies dimensionality change by forming contact plugs that extend in the vertical direction (third direction perpendicular to first and second directions) through multiple interlayer insulating films. This vertical extension allows electrical connections to be established across multiple layers without increasing the horizontal footprint, thereby maintaining high integration while ensuring reliable electrical connections through adequate contact length and surface area.
Solution Approach 2:
The patent implements nesting by placing contact plugs within contact holes formed through interlayer insulating films, and positioning wiring pads on top of contact plugs. This nested structure allows multiple functional elements to be stacked vertically in a compact arrangement, achieving high integration while maintaining proper electrical connections and signal integrity at each level.
2Productivity
If the spacing between word lines is reduced to increase integration, then more elements fit in the same area, but the stability and performance of the device deteriorate
Solution Approach 1:
The patent resolves this contradiction by transitioning to vertical connectivity through contact plugs that extend through multiple interlayer insulating films in the third direction. This allows reduced horizontal spacing between word lines while maintaining stable electrical connections through the vertically extended contact structure, which provides adequate contact length and surface area for reliable signal transmission despite compact horizontal arrangement.
Solution Approach 2:
The patent applies segmentation by dividing the device into distinct functional areas (cell area and peripheral area) and using multiple interlayer insulating films to separate different electrical levels. This segmentation allows independent optimization of each layer while maintaining overall device stability through proper electrical isolation and controlled connections between layers.
3Reliability
If contact plugs extend through multiple interlayer insulating films to ensure reliable connections, then electrical connection reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies merging by forming both the contact plug and the contact hole in a single etching and filling process sequence. The contact plug is formed by etching contact holes through multiple interlayer insulating films and then filling them with conductive material in one integrated process flow, rather than treating each layer separately. This reduces manufacturing complexity while ensuring reliable vertical electrical connections through the stacked structure.
4Ease of manufacture
If the vertical level of wiring pads is aligned with the upper surface of the upper electrode, then coplanarity is achieved simplifying subsequent processing, but the contact plug length must be precisely controlled
Solution Approach 1:
The patent applies equipotentiality by aligning the vertical level of the wiring pad surface with the upper surface of the upper electrode, creating a coplanar configuration. This is achieved by controlling the etching depth and filling height of the contact plug so that the top surface of the contact plug (and the wiring pad formed on it) is at the same level as the upper electrode surface, simplifying subsequent planarization and wiring processes while requiring precise control of the contact plug formation parameters.
Data Source
AI summary
A semiconductor memory device includes a substrate, a capacitor structure including a lower electrode electrically connected to a storage pad, a capacitor dielectric film, and an upper electrode, a cell metal contact contacting an upper surface of the upper electrode, a first peripheral contact plug electrically connected to the substrate, a first peripheral wiring pad in a first interlayer insulating film on the storage pad, a second peripheral contact plug electrically connected to the first peripheral wiring pad, a second peripheral wiring pad contacting the second peripheral contact plug, and a peripheral metal contact electrically connected to the second peripheral wiring pad, wherein a vertical surface of the second peripheral wiring pad is at a level of the upper surface of the upper electrode, and a bottom surface level of the capacitor structure is at a vertical level of an upper surface of the first peripheral wiring pad.