Memory Capacitor Upper Electrode Structure for Reliable Contact Plugs
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Solution Overview
Problem
The miniaturization and lightweighting of electronic devices require a high degree of integration in semiconductor memory devices, making it challenging to secure the reliability of these devices due to reduced design rules for components.
Innovation Solution
A semiconductor memory device design that includes a substrate with a cell area and peripheral area, featuring capacitors with specific electrode structures, etch stop layers, insulation layers, and wiring contact plugs to ensure electrical connectivity and reliability, utilizing a combination of semiconductor and metallic materials in the upper electrode layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If design rules for components are reduced to achieve high degree of integration, then miniaturization and lightweighting of electronic devices is achieved, but reliability of semiconductor memory device deteriorates
Solution Approach 1:
The upper electrode uses a composite structure with a first upper electrode layer (semiconductor material) and a second upper electrode layer (metallic material), combining the advantages of both materials to maintain reliability while achieving miniaturization
Solution Approach 2:
Different regions of the electrode structure use different materials optimized for their specific functions: semiconductor material for the lower electrode layer and metallic material for the upper electrode layer, allowing each region to contribute to overall reliability
Data Source
AI summary
A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.