Stacked Memory Capacitor Structure for Edge Stress Relief
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Solution Overview
Problem
High-density semiconductor memory devices with stacked capacitors face structural damages and reliability issues due to stress susceptibility, which affects their performance and integrity.
Innovation Solution
The capacitors in the semiconductor memory device are fabricated with tilted sidewalls and misaligned upper portions to alleviate stress, using a middle supporting layer to define upper and lower portions, and a planarization layer to adjust stress, reducing structural damage and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked capacitors are formed with increased vertical heights to increase capacitance, then device performance is improved, but structural damages and reliability are degraded due to higher stress impact
Solution Approach 1:
The capacitor array structure employs asymmetric design by tilting capacitors near the sidewall of the array structure. This tilting creates an asymmetric stress distribution that alleviates concentrated stress in critical regions, thereby improving reliability while maintaining the high capacitance achieved through increased vertical heights
Solution Approach 2:
The invention applies local quality by selectively tilting only the capacitors near the sidewall of the capacitor array structure, while other capacitors may remain upright. This localized modification targets the specific region where stress concentration occurs, optimizing stress relief without compromising the overall capacitance performance of the entire array
2Reliability
If stacked capacitors are formed with increased vertical heights to increase capacitance, then device performance is improved, but structural damages occur due to higher stress impact
Solution Approach 1:
The asymmetric tilting of sidewall capacitors creates a stress-relief mechanism that prevents stress-induced damages. The tilted configuration redistributes mechanical stresses away from vulnerable regions, reducing the occurrence of structural damages while preserving the high-capacitance design
Solution Approach 2:
The tilting design acts as a preventive measure that cushions against potential stress-induced damages before they occur. By pre-configuring the capacitor array with tilted sidewall capacitors, the structure is prepared to withstand stress impacts that would otherwise cause structural damages in conventional upright designs
Data Source
AI summary
A semiconductor memory device includes a substrate, and a plurality of contact pads and a capacitor array structure disposed on an array region of the substrate. The capacitor array structure includes a plurality of capacitors respectively disposed on the contact pads and a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors. The lower portions of the capacitors near the edge of the array region are tilted. The upper portions of the capacitors near the edge of the array region have misalignments to the contact pads. The stress in the capacitor array structure of the semiconductor memory device may be reduced.