Memory Capacitor Fabrication with Post-Thermal High-k Deposition
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Solution Overview
Problem
High-temperature processes in semiconductor manufacturing can degrade high-k dielectric materials used in memory device capacitors, leading to reduced capacitance and reliability issues, which limits the scalability and performance of memory devices.
Innovation Solution
Employing a sacrificial material during high-temperature processes and removing it afterward, allowing for the deposition of high-k material without exposure to high temperatures, thereby maintaining its dielectric constant and improving capacitor quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-k dielectric material is used in capacitors during high-temperature processes, then capacitor density and storage capacity can be improved, but the dielectric material degrades leading to reduced reliability and capacitance
Solution Approach 1:
The patent applies preliminary action by performing all high-temperature processes (such as CMOS fabrication steps requiring temperatures above 400°C) before depositing the high-k dielectric material. This sequencing ensures the high-k material is never exposed to high temperatures that would cause degradation, while still allowing the use of high-k material to achieve high capacitance in the final capacitor structure.
2Ease of manufacture
If high-k dielectric material is exposed to high-temperature processes, then manufacturing processes can be completed, but the dielectric constant decreases and capacitor performance deteriorates
Solution Approach 1:
The patent sequences the manufacturing process to complete all high-temperature fabrication steps before depositing the high-k dielectric material. This preliminary completion of thermal processes protects the dielectric constant of the high-k material while still allowing full manufacturing capability to be utilized.
Solution Approach 2:
The patent introduces low-k dielectric material as an intermediary layer between the high-k dielectric material and the high-temperature processing environment. This intermediary protects the high-k material from thermal degradation while allowing the manufacturing process to proceed, effectively mediating between the conflicting requirements of high-temperature processing and high-k material stability.
3Ease of manufacture
If planar memory cell scaling is continued, then manufacturing costs can be reduced, but process technology limitations and reliability issues arise
Solution Approach 1:
The patent transitions from two-dimensional planar capacitor structures to three-dimensional vertical capacitor structures. This dimensional change allows continued scaling and cost reduction while maintaining reliability, as the vertical architecture reduces the area required per capacitor and enables higher density without the same scaling limitations that plague planar designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of high-quality capacitors with increased capacitance and improved reliability, facilitating higher memory density and reduced manufacturing costs by preventing high-k dielectric failure, thus enhancing the performance and storage capacity of memory devices.
Implementation Method 1
removing the sacrificial material to expose the first electrodes
Implementation Method 2
depositing the isolation layer on the first electrodes
Data Source
AI summary
Methods for fabricating memory devices including capacitors are disclosed. In one aspect, a method of fabricating a memory device including capacitors is described, where each capacitor includes a first electrode and a second electrode separated by an isolation layer. The method includes providing a first wafer including a sacrificial material and the first electrodes disposed in first holes and in contact with the sacrificial material, hybrid bonding the first wafer with a second wafer including a complementary metal-oxide-semiconductor (CMOS) device, removing the sacrificial material to expose the first electrodes, depositing the isolation layer on the first electrodes, and forming the second electrodes on the isolation layer.