Semiconductor Memory Capacitor Hole Formation for Reliable Scaling
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Solution Overview
Problem
The increasing demand for compact and lightweight electronic devices has led to a need for highly integrated semiconductor memory devices, making it challenging to ensure the reliability of these devices due to decreasing design rules for their components.
Innovation Solution
A method of manufacturing a semiconductor memory device that involves forming a channel structure, a silicide material layer, a sacrificial semiconductor layer, and a mold layer on a substrate. The sacrificial semiconductor layer is removed to form a capacitor hole, which is filled with a lower electrode. The mold layer is then removed, and a capacitor dielectric layer and an upper electrode are formed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design rules for components are decreased to achieve high integration, then device integration is improved, but reliability of the device deteriorates
Solution Approach 1:
The capacitor structure is divided into multiple layers including a lower electrode, capacitor dielectric layer, and upper electrode, with each layer serving a specific function. The sacrificial semiconductor layer is segmented into multiple sub-layers that can be independently controlled and removed, allowing precise formation of the capacitor hole while maintaining overall device reliability despite reduced design rules
Solution Approach 2:
The sacrificial semiconductor layer is formed in advance with a specific horizontal width before the capacitor hole formation process. This preliminary structure ensures that when the sacrificial layer is removed, a properly sized capacitor hole is created that maintains reliable electrical connection, even when overall device dimensions are reduced for high integration
2Length of moving object
If the horizontal width of the sacrificial semiconductor layer is reduced for miniaturization, then device size is improved, but capacitance of the capacitor structure deteriorates
Solution Approach 1:
The capacitor structure compensates for reduced horizontal width by extending in the vertical dimension. The multi-layer construction with lower electrode, capacitor dielectric layer, and upper electrode creates a vertically extended capacitance path, allowing sufficient capacitance to be maintained even when the horizontal footprint is reduced for miniaturization
Solution Approach 2:
The capacitor dielectric layer uses high-k dielectric materials that provide higher capacitance density, allowing the capacitor structure to achieve required capacitance values with smaller horizontal dimensions. The composite structure of different materials (electrode materials, dielectric materials) enables maintaining capacitance while reducing overall device size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the reliability of semiconductor memory devices by securing the capacitance of the capacitor structure, ensuring the connection structure is exposed through the capacitor hole, and maintaining the constant horizontal width of the sacrificial semiconductor layer, which enhances the device's performance and reliability.
Implementation Method 1
performing a metal-induced crystallization to convert the plurality of silicide material layers into a plurality of induced silicide material layers having a circular planar shape
Data Source
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Figure 2B
AI summary
A method of manufacturing a semiconductor memory device includes forming, on a substrate, a channel structure including a channel pattern; forming, on the channel structure, a silicide material layer including an alloy of a semiconductor material and a metal including a eutectic composition; forming a sacrificial semiconductor layer between the channel structure and the silicide material layer and forming a mold layer surrounding the sacrificial semiconductor layer; forming a capacitor hole by removing the sacrificial semiconductor layer; forming a lower electrode that fills the capacitor hole; removing the mold layer; forming a capacitor dielectric layer that covers a surface of the lower electrode; and forming an upper electrode that covers the capacitor dielectric layer.