Memory Structure With Substrate-Embedded Capacitor Extensions
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Solution Overview
Problem
Current memory structures face challenges in enhancing electrical performance without increasing the size of the memory cell, particularly in integrating transistors and capacitors effectively.
Innovation Solution
The memory structure incorporates extension portions of the capacitor that extend into the substrate at both sides of the isolation structure, increasing the coupling ratio between the bottom and top electrodes without expanding the layout area, achieved through a manufacturing method involving trench formation and etching processes that control the width and depth of these extensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitor is configured with extension portions extending into the substrate at both sides of the isolation structure, then the coupling area between electrodes is increased and electrical performance is improved, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
The capacitor structure transitions from a planar configuration to a three-dimensional configuration by extending the capacitor body portion downward into the substrate. This vertical extension into the substrate dimension increases the coupling area between electrodes without expanding the lateral layout area, thereby improving electrical performance while maintaining compact footprint.
Solution Approach 2:
The extension portions of the capacitor are nested within the substrate volume by extending into the substrate at both sides of the isolation structure. This nesting approach allows the capacitor to utilize the substrate space efficiently, increasing the coupling area without occupying additional lateral space that would increase layout area.
2Reliability
If the extension portions of the capacitor extend into the substrate, then the coupling ratio between bottom and top electrodes is increased, but the manufacturing precision requirements increase due to controlled width and depth
Solution Approach 1:
The width of the extension portions is designed to decrease downward from the top surface of the isolation structure. This parameter change in width along the vertical dimension allows for increased coupling area while managing manufacturing precision requirements, as the tapering geometry provides manufacturing tolerance benefits compared to vertical walls.
Solution Approach 2:
The capacitor structure exhibits local quality variations where the extension portions have different width characteristics at different depths. The width decreases downward from the top surface of the isolation structure, creating a tapered geometry that optimizes both coupling ratio and manufacturability by distributing stress and easing fabrication constraints.
3Area of stationary object
If the capacitor body portion is disposed above the isolation structure with extension portions at both sides, then the coupling area is increased without increasing layout area, but the device structure complexity increases
Solution Approach 1:
The capacitor utilizes the vertical dimension by extending into the substrate, allowing the coupling area to increase without increasing the lateral layout area. The body portion is disposed above the isolation structure with extension portions extending downward, effectively using the Z-axis to achieve area expansion.
Solution Approach 2:
The capacitor is segmented into distinct portions: a body portion disposed above the isolation structure and extension portions extending into the substrate at both sides of the isolation structure. This segmentation allows each portion to serve specific functions while collectively achieving increased coupling area within the same layout footprint.
Data Source
AI summary
A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.