3D Memory Capacitor Structure With Supporting Layers for Easier Deposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The continuous reduction in device size increases the aspect ratio of openings in semiconductor memory devices, making it difficult to further increase capacitor capacitance due to fabricating challenges in filling dielectric layers and upper electrodes.
Innovation Solution
A semiconductor memory device structure is implemented with a substrate, first and second high-k dielectric layers, and supporting layers, where the first electrodes have high-k dielectric layers on their sidewalls, and the second electrode is placed on the second high-k dielectric layer, with supporting layers between adjacent first electrodes to provide lateral support and isolate them, allowing for larger openings and easier deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the device size is continuously reduced, then the integration density is improved, but the aspect ratio of openings increases making fabrication difficult
Solution Approach 1:
The patent transitions from conventional planar capacitor structures to vertically stacked 3D capacitor structures. Multiple capacitor stacks are formed vertically above each other, utilizing the third dimension (height) to increase capacitance without increasing planar footprint. This dimensional change allows continued scaling while maintaining manufacturability by avoiding excessively high aspect ratios in single openings.
Solution Approach 2:
The capacitor structure is segmented into multiple independent capacitor stacks, each with its own electrode assembly and dielectric layers. These stacks are formed in separate openings but connected through shared supporting layers and common electrode structures, allowing each opening to have manageable dimensions while achieving total capacitance through the sum of multiple stacked capacitors.
2Area of stationary object
If the opening size is reduced to increase capacitor density, then the capacitance per area is improved, but the aspect ratio increases making deposition difficult
Solution Approach 1:
The patent forms capacitor stacks vertically extending through multiple dielectric layers, increasing the effective capacitance area in the vertical dimension rather than compressing everything into a single planar layer. This allows maintaining reasonable opening dimensions for deposition while achieving high capacitance density through the stacked configuration.
Solution Approach 2:
Multiple dielectric layers and electrode structures are nested vertically within each other to form capacitor stacks. Each capacitor stack contains nested layers of electrodes and dielectrics, with supporting layers providing structural framework. This nesting allows efficient use of vertical space for deposition processes.
Data Source
AI summary
The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.