Memory Card Interface Clock Recovery for Fast Dormant Wake-Up
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Solution Overview
Problem
In UHS-II/-III memory card interfaces, the stabilization of the inner clock frequency after a state transition from dormant to active leads to increased latency due to the need for a handshake check, and maintaining the PLL circuit in an operating state during dormancy increases power consumption.
Innovation Solution
An interface system that stops the reference clock supply during dormancy and omits the handshake check upon returning to the active state, utilizing a control voltage memory unit to rapidly lock the PLL and CDR circuits, reducing standby power and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference clock is continuously supplied during dormancy to maintain PLL circuit operation, then the clock synchronization stability is improved, but the standby power consumption increases
Solution Approach 1:
The reference clock is supplied periodically rather than continuously - it is stopped during dormancy and restarted when needed. The PLL circuit performs rapid phase locking when the clock is restarted, enabling periodic operation that reduces power consumption while maintaining synchronization capability when required.
Solution Approach 2:
The control voltage memory unit stores the control voltage that corresponds to the locked state of the PLL circuit before dormancy occurs. When the reference clock is restarted, this pre-stored control voltage is immediately applied to the PLL, enabling rapid phase locking without requiring the full stabilization time that would otherwise be needed.
2Reliability
If the handshake check is performed upon state transition from dormant to active, then the data transfer reliability is improved, but the latency increases
Solution Approach 1:
The control voltage memory unit performs preliminary action by storing the control voltage that corresponds to the locked state before the system enters dormancy. When transitioning to active state, this pre-stored voltage is immediately applied to the PLL circuit, enabling rapid phase locking and eliminating the need for time-consuming handshake checks, thus reducing latency while maintaining reliability.
Solution Approach 2:
The system uses a copy of the control voltage (stored in memory) instead of requiring the full phase locking process to occur again. The stored control voltage is a representation of the locked state that can be rapidly reapplied, serving as a substitute for the time-consuming handshake verification process.
3Duration of action of moving object
If the PLL circuit is maintained in operating state during dormancy, then the clock stabilization time is reduced, but the power consumption increases
Solution Approach 1:
The PLL circuit operates periodically rather than continuously - it is stopped during dormancy and restarted when needed. The combination of periodic operation with rapid phase locking (enabled by pre-stored control voltage) achieves a balance where the circuit consumes minimal power during dormancy but can stabilize quickly when activated.
Solution Approach 2:
The control voltage memory unit captures and stores the control voltage corresponding to the locked state before dormancy. This preliminary action allows the PLL circuit to skip the lengthy stabilization period during wake-up, achieving fast clock stabilization without requiring continuous operation during dormancy, thus resolving the contradiction between stabilization time and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes standby power consumption and enables rapid recovery from a dormant state to an active state without increasing latency, allowing immediate data transfer after a short period.
Implementation Method 1
The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock
Data Source
AI summary
According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.