Memory Card Data Control Circuit Double-Edge Clock Synchronization

Solution Overview

Problem

Current SD memory cards face challenges in enhancing data transfer speed due to increased noise and complexity at higher clock rates, and increased costs with wider bus widths, while existing techniques struggle to efficiently manage these improvements.

Innovation Solution

A memory card and host device configuration that employs a data control circuit for double-edge clock synchronization in data transfer and single-edge synchronization for command/response operations, allowing for enhanced data transfer speed without increasing clock rate or pin count, using a switch command to toggle between modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the transfer clock rate is enhanced to increase data transfer speed, then data transfer speed is improved, but noise influence increases and timing definition becomes severe

Engineering Contradiction:

Improvedata transfer speedVSAvoidnoise influence

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent changes the timing parameter by utilizing both rise edge and fall edge of the clock signal for data sampling, effectively doubling the data transfer rate without increasing the clock frequency. This allows achieving higher data transfer speed while maintaining the original clock rate, thereby avoiding the noise and timing definition problems associated with higher clock rates

Inventive Principle:

Principle #35Parameter changes

2Speed

If the bus width is increased to increase data transfer speed, then data transfer speed is improved, but the cost rises due to increased number of input/output pins

Engineering Contradiction:

Improvedata transfer speedVSAvoidmanufacturing cost

Core Design Contradiction:

SpeedVSEase of manufacture

Solution Approach 1:

The patent changes the timing parameter by utilizing both rise edge and fall edge of the clock signal for data sampling, effectively doubling the data transfer rate without increasing the clock frequency. This allows achieving higher data transfer speed while maintaining the original clock rate, thereby avoiding the noise and timing definition problems associated with higher clock rates

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11922022B2Method for transferring data on a memory card in synchronism with a rise edge and a fall edge of a clock signal

Publication Date: 2024.03.05 KIOXIA CORP

AI summary

A method of controlling a storage device including a command terminal, a plurality of data terminals, and a clock terminal, including receiving a clock signal through the clock terminal; outputting a first status data through the data terminals in accordance with only one of a rising edge and a falling edge of the clock signal in a first transfer mode; outputting data through the data terminals in accordance with both the rising edge and the falling edge of the clock signal in a second transfer mode; and receiving and responding to commands via the command terminal in accordance with only one of a rising edge and a falling edge of the clock signal while outputting data through the data terminals in accordance with both the rising edge and the falling edge of the clock signal in the second transfer mode.