Semiconductor Memory Card Erase Block Control for Write Speed
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Solution Overview
Problem
Conventional semiconductor memory cards require a two-stage operation for data rewriting, leading to inefficiencies and prolonged writing times due to parallel erasure processes that are not size-dependent, especially for small data sizes, resulting in increased overall writing time.
Innovation Solution
A semiconductor memory card system that includes a memory controller capable of determining the number of erase blocks based on the write start address and size, allowing for selective erasure of invalid blocks and simultaneous writing and erasing operations across nonvolatile memory chips, optimizing processing performance and reducing unnecessary erasure time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erasing is performed in parallel regardless of data size, then erasing can be performed simultaneously in multiple memory chips, but it takes lots of time for small data sizes and increases overall writing time
Solution Approach 1:
The patent changes the parameter of erase block count from a fixed value to a dynamically adjustable value based on data size. When data size is small, the system reduces or eliminates parallel erase operations, and when data size is large, it increases the number of parallel erase operations. This parameter adaptation resolves the contradiction by making erase time proportional to actual writing needs.
Solution Approach 2:
The system dynamically adjusts the erase strategy based on real-time conditions including data size, number of valid blocks in target address range, and availability of free blocks. This dynamic control allows the system to switch between different operational modes: performing erases in parallel only when necessary, skipping erases when free blocks are sufficient, and adjusting the degree of parallelism according to workload characteristics.
2Reliability
If a two-stage operation is performed where data is first erased and then written, then data can be rewritten, but much time is consumed until finishing writing completely
Solution Approach 1:
The system performs preliminary assessment of erase requirements before actual writing begins. By evaluating the number of valid blocks in the target address range and comparing against free block availability, the system determines in advance whether erases are needed and how many should be performed in parallel. This preliminary action prevents unnecessary sequential operations and optimizes the overall writing time while maintaining data integrity.
Solution Approach 2:
The patent enables continuous useful action by allowing write operations to proceed without waiting for complete erase completion when free blocks are available. The system continuously monitors block availability and dynamically assigns write operations to free blocks or initiates erases only when necessary, eliminating idle waiting time and maintaining continuous productive operation throughout the writing process.
Data Source
AI summary
A host information memory is provided in a semiconductor memory card and a data write start address and a data size supplied by an access unit are stored. A free physical area generation section determines whether or not to perform erasing of an invalid block of a nonvolatile memory when writing of data based on the data write start address and data size, and determines the number of blocks to be erased. When erasing, writing of data and erasing of invalid blocks are simultaneously performed with respect to different memory chips. Erase process of data, herewith, can be optimized and high speed access from the access unit to a semiconductor memory card can be realized.