Semiconductor Memory Card Stacking with Long-Side Electrode Pads
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Solution Overview
Problem
The challenge is to increase the capacity and integration of memory chips on a memory card while maintaining a compact size, as existing stacked structures with electrode pads along short sides lead to increased occupied area and difficulty in connecting multiple memory chips, restricting the number of chips that can be mounted on a wiring board.
Innovation Solution
A semiconductor memory device with a wiring board featuring a rectangular shape and multiple chip groups stacked in a step-like fashion, with electrode pads biased towards short sides to optimize connection areas, and metal wires connecting pads on the wiring board to exposed electrode pads, allowing for increased chip density and capacity without expanding the card's dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory chips are stacked in a step-like shape with electrode pads along short sides, then wire bonding can be performed, but the occupied area increases and the number of mountable chips is restricted
Solution Approach 1:
The patent transitions from stacking chips with pads along short sides to stacking chips with pads along long sides. This dimensional reorientation allows chips to be arranged more efficiently in the stacking direction, reducing the occupied area on the wiring board while maintaining wire bonding capability. The long-side pad configuration enables better space utilization in the planar direction.
Solution Approach 2:
The patent employs asymmetric stacking where chips in different groups are positioned at different heights and orientations. The first chip group has chips stacked with pads along one long side, while the second chip group has chips stacked with pads along the opposite long side, creating an asymmetric but space-efficient arrangement that maximizes the number of mountable chips.
2Quantity of substance
If the number of memory chips is increased for high capacity, then card capacity improves, but the card size increases beyond specified standards
Solution Approach 1:
The patent utilizes the vertical stacking dimension to increase chip capacity without expanding the card's planar footprint. By stacking multiple chips in layers along the vertical axis and using long-side pad configurations, the system accommodates more chips within the standardized card dimensions specified by SDTM standards.
Solution Approach 2:
The patent implements a nested stacking structure where multiple chip groups are arranged in layers, with each group containing multiple chips stacked vertically. This nested arrangement allows high-density integration of memory chips while maintaining compliance with external card size specifications.
3Quantity of substance
If memory chips are provided with higher integration for high capacity, then chip capacity increases, but the outer shape of the chip becomes large
Solution Approach 1:
The patent addresses the chip size issue by orienting electrode pads along the long sides of rectangular chips rather than short sides. This orientation allows for more efficient vertical stacking and better utilization of the chip's dimensional space, enabling higher integration capacity without excessive increase in the chip's outer dimensions.
4Ease of manufacture
If a single-long-side pad structure is used, then connection area is optimized, but the structure cannot comply with increased number of electrodes for high integration
Solution Approach 1:
The patent creates an asymmetric two-group stacking structure where the first chip group and second chip group are positioned differently in the vertical direction and have pads oriented along opposite long sides. This asymmetric arrangement provides flexible connection paths and sufficient connection area while accommodating an increased number of electrodes required for high-integration, high-capacity memory systems.
Data Source
AI summary
A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.